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M95020-WBN3TP Datasheet(PDF) 5 Page - STMicroelectronics |
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M95020-WBN3TP Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 37 page 5/37 M95040, M95020, M95010 SUMMARY DESCRIPTION The M95040 is a 4 Kbit (512 x 8) electrically eras- able programmable memory (EEPROM), access- ed by a high speed SPI-compatible bus. The other members of the family (M95020 and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial inter- face that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2. and Figure 2.. The device is selected when Chip Select (S) is tak- en Low. Communications with the device can be interrupted using Hold (HOLD). WRITE instruc- tions are disabled by Write Protect (W). Figure 2. Logic Diagram Figure 3. DIP, SO and TSSOP Connections Note: See PACKAGE MECHANICAL section for package dimen- sions, and how to identify pin-1. Table 2. Signal Names AI01789C S VCC M95xxx HOLD VSS W Q C D C Serial Clock D Serial Data Input Q Serial Data Output S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground D VSS C HOLD Q SVCC W AI01790D M95xxx 1 2 3 4 8 7 6 5 |
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