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V436664S24VXTG-10PC Datasheet(PDF) 5 Page - Mosel Vitelic, Corp |
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V436664S24VXTG-10PC Datasheet(HTML) 5 Page - Mosel Vitelic, Corp |
5 / 12 page MOSEL VITELIC V436664S24V 5 V436664S24V Rev. 1.1 March 2002 DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V 28 Minimum Row Active to Row Active Delay tRRD 14 ns/15 ns/16 ns 0E 0F 10 29 Minimum RAS to CAS Delay tRCD 15 ns/20 ns 0F 14 14 30 Minimum RAS Pulse Width tRAS 42 ns/45 ns 2A 2D 2D 31 Module Bank Density (Per Bank) 256 MByte 40 40 40 32 SDRAM Input Setup Time 1.5 ns/2.0 ns 15 15 20 33 SDRAM Input Hold Time 0.8 ns/1.0 ns 08 08 10 34 SDRAM Data Input Setup Time 1.5 ns/2.0 ns 15 15 20 35 SDRAM Data Input Hold Time 0.8 ns/1.0 ns 08 08 10 36-61 Superset Information (May be used in Fu- ture) 00 00 00 62 SPD Revision Revision 2/1.2 02 02 12 63 Checksum for Bytes 0 - 62 FE 43 B1 64 Manufacturer’s JEDEC ID Code Mosel Vitelic 40 40 40 65-71 Manufacturer’s JEDEC ID Code (cont.) 00 00 00 72 Manufacturing Location 73-90 Module Part Number (ASCII) V436664S24V 91-92 PCB Identification Code 93 Assembly Manufacturing Date (Year) 94 Assembly Manufacturing Date (Week) 95-98 Assembly Serial Number 99-125 Reserved 00 00 00 126 Intel Specification for Frequency 64 64 64 127 Reserved 128+ Unused Storage Location 00 00 00 Symbol Parameter Limit Values Unit Min. Max. VIH Input High Voltage 2.0 VCC+0.3 V VIL Input Low Voltage –0.5 0.8 V VOH Output High Voltage (IOUT = –2.0 mA) 2.4 — V SPD-Table : (Continued) Byte Num- ber Function Described SPD Entry Value Hex Value -75PC -75 -10PC |
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