10

LTC1860/LTC1861

18601f

Figure 4. LTC1861 Operating Sequence

MUX ADDRESS

Table 1. Multiplexer Channel Selection

SGL/DIFF

1

1

0

0

ODD/SIGN

0

1

0

1

CHANNEL #

0

+

+

–

1

+

–

+

GND

–

–

186465 TBL1

SINGLE-ENDED

MUX MODE

DIFFERENTIAL

MUX MODE

CONV

SDI

SCK

12

11

10

9

8

7

6

5

4

3

2

1

SDO

B11 B10

B8B6

B4B2

B0*

Hi-Z

B9

B7

B5

B3

B1

S/D O/S

DON’T CARE

DON’T CARE

1860 F04

SLEEP MODE

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE

APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY

Hi-Z

Figure 5. LTC1861 Transfer Curve

(SELECTED “–” CHANNEL)

REFER TO TABLE 1

0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 0

•

•

•

1860 F05

APPLICATIO S I FOR ATIO

GENERAL ANALOG CONSIDERATIONS

Grounding

The LTC1860/LTC1861 should be used with an analog

ground plane and single point grounding techniques. Do

not use wire wrapping techniques to breadboard and

evaluate the device. To achieve the optimum performance,

use a printed circuit board. The ground pins (AGND and

DGND for the LTC1861 MSOP package and GND for the

LTC1860 and LTC1861 SO-8 package) should be tied

directly to the analog ground plane with minimum lead

length.

Bypassing

with respect to ground during the conversion cycle can

minimum of 1

µF tantalum. Keep the bypass capacitor

leads as short as possible.

Analog Inputs

Because of the capacitive redistribution A/D conversion

techniques used, the analog inputs of the LTC1860/

LTC1861 have capacitive switching input current spikes.

These current spikes settle quickly and do not cause a

problem if source resistances are less than 200

Ω or high

speed op amps are used (e.g., the LT

LT1807, LT1810, LT1630, LT1226 or LT1215). But if large

source resistances are used, or if slow settling op amps

drive the inputs, take care to ensure the transients caused

by the current spikes settle completely before the conver-

sion begins.