V43728S04VCTG-75 datasheet(4/12 Pages) MOSEL

Part #	V43728S04VCTG-75

Description	3.3 VOLT 8M x 72 HIGH PERFORMANCE PC133 UNBUFFERED ECC SDRAM MODULE

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Manufacturer	MOSEL [Mosel Vitelic, Corp]

Direct Link	http://www.moselvitelic.com

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V43728S04V(C)TG-75 Rev. 1.2 September 2000

MOSEL VITELIC

V43728S04V(C)TG-75

Serial Presence Detect Information

A serial presence detect storage device -

E2PROM

-

is

assembled

onto

the

module.

Information about the module configuration, speed,

etc. is written into the E2PROM device during

module production using a serial presence detect

protocol (I2C synchronous 2-wire bus)

SPD-Table for PC133 modules:

Byte Number

Function Described

SPD Entry Value

Hex Value

8Mx72

0

Number of SPD bytes

128

80

1

Total bytes in Serial PD

256

08

2

Memory Type

SDRAM

04

3

Number of Row Addresses (without BS bits)

12

0C

4

Number of Column Addresses (for x8 SDRAM)

9

09

5

Number of DIMM Banks

1

01

6

Module Data Width

72

48

7

Module Data Width (continued)

0

00

8

Module Interface Levels

LVTTL

01

9

SDRAM Cycle Time at CL=3

7.5 ns

75

10

SDRAM Access Time from Clock at CL=3

5.4 ns

54

11

Dimm Config (Error Det/Corr.)

ECC

02

12

Refresh Rate/Type

Self-Refresh, 15.6

µs

80

13

SDRAM width, Primary

x8

08

14

Error Checking SDRAM Data Width

n/a / x8

08

15

Minimum Clock Delay from Back to Back Random

Column Address

tccd = 1 CLK

01

16

Burst Length Supported

1, 2, 4, 8 & full Page

8F

17

Number of SDRAM Banks

4

04

18

Supported CAS Latencies

CL = 3

04

19

CS Latencies

CS Latency = 0

01

20

WE Latencies

WL = 0

01

21

SDRAM DIMM Module Attributes

Non Buffered/Non Reg.

00

22

SDRAM Device Attributes: General

Vcc tol

± 10%

0E

23

Minimum Clock Cycle Time at CAS Latency = 2

Not Supported

00

24

Maximum Data Access Time from Clock for CL = 2

Not Supported

00

25

Minimum Clock Cycle Time at CL = 1

Not Supported

00

26

Maximum Data Access Time from Clock at CL = 1

Not Supported

00

27

Minimum Row Precharge Time

20 ns

14

28

Minimum Row Active to Row Active Delay tRRD

15 ns

0F

29

Minimum RAS to CAS Delay tRCD

20 ns

14

30

Minimum RAS Pulse Width tRAS

45 ns

2D

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V43728S04VCTG-75 Datasheet(PDF) 4 Page - Mosel Vitelic, Corp

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