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BQ24380DSGR Datasheet(PDF) 11 Page - Texas Instruments |
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BQ24380DSGR Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 18 page  APPLICATION INFORMATION Selection of R(BAT) Selection of R(CE) Selection of Input and Output Bypass Capacitors PCB Layout Guidelines bq24380 bq24381 www.ti.com .............................................................................................................................................................. SLUS805A – APRIL 2008 – REVISED MAY 2008 It is recommended that the battery not be tied directly to the VBAT pin of the device, as under some failure modes of the IC, the voltage at the IN pin may appear on the VBAT pin. This voltage can be as high as 30 V, and applying 30 V to the battery may cause failure of the device and can be hazardous. Connecting the VBAT pin through R(BAT) prevents a large current from flowing into the battery in the event of failure. For safety, R(BAT) must have a high value. The problem with a large R(BAT) is that the voltage drops across the resistor because of the VBAT bias current, I(VBAT), which causes an error in the BVOVP threshold. This error is over and above the tolerance on the nominal 4.35-V BVOVP threshold. Choosing R(BAT) in the range of 100 kΩ to 470 kΩ is a good compromise. If the IC fails with R(BAT) equal to 100 k Ω, the maximum current flowing into the battery would be (30 V – 3 V) ÷ 100 kΩ = 246 µA, which is low enough to be absorbed by the bias currents of the system components. R(BAT) equal to 100 kΩ results in a worst-case voltage drop of R(BAT) × I(VBAT) ≈ 1 mV. This is negligible compared to the internal tolerance of 50 mV on the BVOVP threshold. If the Bat-OVP function is not required, the VBAT pin must be connected to VSS. The CE pin can be used to enable and disable the IC. If host control is not required, the CE pin can be tied to ground or left unconnected, permanently enabling the device. In applications where external control is required, the CE pin can be controlled by a host processor. As with the VBAT pin (see previous discussion), the CE pin must be connected to the host GPIO pin through as large a resistor as possible. The limitation on the resistor value is that the minimum VOH of the host GPIO pin less the drop across the resistor must be greater than VIH of the bq2430x CE pin. The drop across the resistor is given by R(CE) × IIH. The input capacitor CIN in Figure 17 is for decoupling and serves an important purpose. Whenever a step change downwards in the system load current occurs, the inductance of the input cable causes the input voltage to spike up. CIN prevents the input voltage from overshooting to dangerous levels. It is recommended that a ceramic capacitor of at least 1 µF be used at the input of the device. It must be located in close proximity to the IN pin. COUT in Figure 17 is also important. During an overvoltage transient, this capacitance limits the output overshoot until the power FET is turned off by the overvoltage protection circuitry. COUT must be a ceramic capacitor of at least 1 µF, located close to the OUT pin. C OUT also serves as the input decoupling capacitor for the charging circuit downstream of the protection IC. 1. This device is a protection device and is meant to protect down-stream circuitry from hazardous voltages. Potentially, high voltages may be applied to this IC. It has to be ensured that the edge-to-edge clearances of PCB traces satisfy the design rules for the maximum voltages expected to be seen in the system. 2. The device uses SON packages with a PowerPAD™. For good thermal performance, the PowerPAD must be thermally coupled with the PCB ground plane. In most applications, this requires a copper pad directly under the IC. This copper pad should be connected to the ground plane with an array of thermal vias. 3. CIN and COUT should be located close to the IC. Other components like R(BAT) should also be located close to the IC. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): bq24380 bq24381 |
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