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DSP56301AG80 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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DSP56301AG80 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 124 page  DSP56301 Technical Data, Rev. 10 1-6 Freescale Semiconductor Signals/Connections 1.5 External Memory Expansion Port (Port A) Note: When the DSP56301 enters a low-power stand-by mode (Stop or Wait), it releases bus mastership and tri- states the relevant Port A signals: A[0–23], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS, BCLK, and BCLK . If hardware refresh of external DRAM is enabled, Port A exits the Wait mode to allow the refresh to occur and then returns to the Wait mode. 1.5.1 External Address Bus 1.5.2 External Data Bus PINIT/NMI Input Input PLL Initial/Non-Maskable Interrupt During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET deassertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered Non-Maskable Interrupt (NMI) request internally synchronized to CLKOUT. PINIT/NMI can tolerate 5 V. Table 1-6. External Address Bus Signals Signal Name Type State During Reset Signal Description A[0–23] Output Tri-stated Address Bus When the DSP is the bus master, A[0–23] specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A[0–23] do not change state when external memory spaces are not being accessed. Table 1-7. External Data Bus Signals Signal Name Type State During Reset Signal Description D[0–23] Input/Output Tri-stated Data Bus When the DSP is the bus master, D[0–23] provide the bidirectional data bus for external program and data memory accesses. Otherwise, D[0–23] are tri- stated. Table 1-5. Phase Lock Loop Signals (Continued) Signal Name Type State During Reset Signal Description |
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