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EDD5116AGTA Datasheet(PDF) 9 Page - Elpida Memory |
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EDD5116AGTA Datasheet(HTML) 9 Page - Elpida Memory |
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9 / 52 page  EDD5108AGTA, EDD5116AGTA Data Sheet E1191E20 (Ver. 2.0) 9 AC Characteristics (TA = 0°C to +70 °C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266] -6B -7A -7B Parameter Symbol min. max. min. max min. max. Unit Notes Clock cycle time (CL = 2) tCK 7.5 12 7.5 12 10 12 ns 10 (CL = 2.5) tCK 6 12 7.5 12 7.5 12 ns CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK half period tHP min (tCH, tCL) — min (tCH, tCL) — min (tCH, tCL) — tCK DQ output access time from CK, /CK tAC –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 2, 11 DQS output access time from CK, /CK tDQSCK –0.6 0.6 –0.75 0.75 –0.75 0.75 ns 2, 11 DQS to DQ skew tDQSQ — 0.45 — 0.5 — 0.5 ns 3 DQ/DQS output hold time from DQS tQH tHP – tQHS — tHP – tQHS — tHP – tQHS — ns Data hold skew factor tQHS — 0.55 — 0.75 — 0.75 ns Data-out high-impedance time from CK, /CK tHZ — 0.7 — 0.75 — 0.75 ns 5, 11 Data-out low-impedance time from CK, /CK tLZ –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 6, 11 Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQ and DM input setup time tDS 0.45 — 0.5 — 0.5 — ns 8 DQ and DM input hold time tDH 0.45 — 0.5 — 0.5 — ns 8 DQ and DM input pulse width tDIPW 1.75 — 1.75 — 1.75 — ns 7 Write preamble setup time tWPRES 0 — 0 — 0 — ns Write preamble tWPRE 0.25 — 0.25 — 0.25 — tCK Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 9 Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK setup time tDSS 0.2 — 0.2 — 0.2 — tCK DQS falling edge hold time from CK tDSH 0.2 — 0.2 — 0.2 — tCK DQS input high pulse width tDQSH 0.35 — 0.35 — 0.35 — tCK DQS input low pulse width tDQSL 0.35 0.35 — 0.35 — tCK Address and control input setup time tIS 0.75 — 0.9 — 0.9 — ns 8 Address and control input hold time tIH 0.75 — 0.9 — 0.9 — ns 8 Address and control input pulse width tIPW 2.2 — 2.2 — 2.2 — ns 7 Mode register set command cycle time tMRD 2 — 2 — 2 — tCK Active to Precharge command period tRAS 42 120000 45 120000 45 120000 ns Active to Active/Auto-refresh command period tRC 60 — 65 — 65 — ns Auto-refresh to Active/Auto-refresh command period tRFC 72 — 75 — 75 — ns Active to Read/Write delay tRCD 18 — 20 — 20 — ns Precharge to active command period tRP 18 — 20 — 20 — ns Active to Autoprecharge delay tRAP tRCD min. — tRCD min. — tRCD min. — ns Active to active command period tRRD 12 — 15 — 15 — ns |
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