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TMS320F206PZA Datasheet(PDF) 4 Page - Texas Instruments |
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TMS320F206PZA Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 58 page  TMS320F206 DIGITAL SIGNAL PROCESSOR SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320F206 Terminal Functions (Continued) TERMINAL TYPE† DESCRIPTION NAME NO. TYPE† DESCRIPTION MEMORY CONTROL SIGNALS (CONTINUED) WE 44 O/Z Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15 – D0). Data can be latched by an external device on the rising edge of WE. WE is active on all external program, data, and I / O writes. WE goes into the high-impedance state when OFF is active low. STRB 46 O/Z Strobe signal. STRB is always high unless asserted low to indicate an external bus cycle. STRB goes into the high-impedance state when OFF is active low. MULTI-PROCESSING SIGNALS BR 43 O/Z Bus-request signal. BR is asserted when a global data-memory access is initiated. BR goes into the high-impedance state when OFF is active low. HOLDA 6 O/Z Hold-acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and that the address, data, and memory control lines are in the high-impedance state so that they are available to the external circuitry for access of local memory. HOLDA goes into the high-impedance state when OFF is active low. XF 98 O/Z External flag output (latched software-programmable signal). XF is used for signalling other processors in multiprocessing configurations or as a general-purpose output pin. XF goes into the high-impedance state when OFF is active low. BIO 99 I Branch control input. When polled by the BIOZ instruction, if BIO is low, the TMS320F206 executes a branch. IO0 IO1 IO2 IO3 96 97 8 9 I / O/Z Software-controlled input / output pins by way of the asynchronous serial-port control register (ASPCR). At reset, IO0–IO3 are configured as inputs. These pins can be used as general-purpose input / output pins or as handshake control for the UART. IO0 – IO3 go into the high-impedance state when OFF is active low. IO0 also functions as a frame-sync output when the synchronous serial port (SSP) is used in multichannel mode. INITIALIZATION, INTERRUPTS, AND RESET OPERATIONS RS 100 I Reset input. RS causes the TMS320F206 to terminate execution and forces the program counter to zero. When RS is brought high, execution begins at location 0 of program memory after 16 cycles. RS affects various registers and status bits. TEST 1 I Reserved input pin. TEST is connected to VSS for normal operation. MP/MC 2 I Microprocessor/microcomputer-mode-select pin. If MP/MC is low, the on-chip flash memory is mapped into program space. When MP/MC is high, the device accesses off-chip memory. This pin is only sampled at reset, and its value is latched into bit 0 of the PMST register. NMI 17 I Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the interrupt-mode bit (INTM) or the interrupt mask register (IMR). When NMI is activated, the processor traps to the appropriate vector location. If NMI is not used, it should be pulled high. HOLD/INT1 18 I HOLD and INT1 share the same pin. Both are treated as interrupt signals. If the MODE bit is 0 in the interrupt-control register (ICR), hold logic can be implemented in combination with the IDLE instruction in software. At reset, the MODE bit in ICR is zero, enabling the HOLD mode for the pin. INT2 INT3 19 20 I External user interrupts. INT2 and INT3 are prioritized and maskable by the IMR and the INTM. INT2 and INT3 can be polled and reset by way of the interrupt flag register (IFR). OSCILLATOR, PLL, AND TIMER SIGNALS TOUT 92 O/Z Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT1-cycle wide. TOUT goes into the high-impedance state when OFF is active low. CLKOUT1 15 O/Z Master clock output signal. The CLKOUT1 signal cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the rising edges of CLKOUT1. CLKOUT1 goes into the high-impedance state when OFF is active low. CLKIN/X2 X1 12 13 I O Input clock. CLKIN/X2 is the input clock to the device. As CLKIN, the pin operates as the external oscillator clock input, and as X2, the pin operates as the internal oscillator input with X1 being the internal oscillator output. † I = input, O = output, Z = high impedance, PWR = power, GND = ground |
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