TMS418169A, TMS428169A

1048576 BY 16-BIT EXTENDED DATA OUT

DYNAMIC RANDOM-ACCESS MEMORIES

SMKS892C – AUGUST 1996 – REVISED SEPTEMBER 1997

4

POST OFFICE BOX 1443

extended data out

Extended data out (EDO) allows for data output rates of up to 50 MHz for 50-ns devices. When keeping the same

row address while selecting random column addresses, the time for row-address setup-and-hold and address

maximum RAS low time.

EDO does not enter the DQs into the high-impedance state with the rising edge of xCAS. The output remains

valid for the system to latch the data. After xCAS goes high, the DRAM decodes the next address. OE and W

can be used to control the output impedance. Descriptions of OE and W further explain the benefit of EDO

operation.

address: A0 – A9

Twenty address bits are required to decode each of the 1 048 576 storage cell locations. Ten row-address bits

are set up on A0 – A9 and latched on the chip by RAS. Ten column-address bits are set up on A0 – A9 and latched

on the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS

is similar to a chip-enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as

a chip-select, activating its corresponding output buffer and latching the address bits into the column-address

buffers.

The column address is latched on the first xCAS falling edge with address setup and hold parameters

referenced to that edge. In order to latch in a new column address, both xCAS pins must be brought high. The

edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum setup time,

write enable ( W )

The read- or write mode is selected through W. A logic high on W selects the read mode and a logic low selects

the write mode. The data input is disabled when the read mode is selected. When W goes low prior to xCAS

(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation

independent of the state of OE. This permits early-write operations to be completed with OE grounded. If W goes

low in an EDO-read cycle, the DQ pins go into the high-impedance state as long as xCAS is high (see Figure 9).

data in (DQ0 – DQ15)

Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the falling edge

of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to an xCAS

falling edge, and data is strobed into the on-chip data latch for the corresponding DQ pins with setup-and-hold

times referenced to this xCAS signal.

In a delayed-write- or read-modify-write cycle, xCAS is already low and data is strobed in by W with

setup-and-hold times referenced to this signal. Also, OE must be high to bring the output buffers to the

data out (DQ0 – DQ15)

Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE

data out is measured from each individual xCAS to its corresponding DQx pin.