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V437316S04VXTG-10PC Datasheet(PDF) 4 Page - Mosel Vitelic, Corp |
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V437316S04VXTG-10PC Datasheet(HTML) 4 Page - Mosel Vitelic, Corp |
4 / 12 page 4 V437316S04V Rev. 1.0 December 2001 MOSEL VITELIC V437316S04V Serial Presence Detect Information A serial presence detect storage device - E2PROM - is assembled onto the module. Informa- tion about the module configuration, speed, etc. is writtenintothe E2PROM device during module pro- duction using a serial presence detect protocol (I2C synchronous 2-wire bus) SPD-Table Byte Num- ber Function Described SPD Entry Value Hex Value -75PC -75 -10PC 0 Number of SPD bytes 128 80 80 80 1 Total bytes in Serial PD 256 08 08 08 2 Memory Type SDRAM 04 04 04 3 Number of Row Addresses (without BS bits) 12 0C 0C 0C 4 Number of Column Addresses (for x8 SDRAM) 10 0A 0A 0A 5 Number of DIMM Banks 1 01 01 01 6 Module Data Width 72 48 48 48 7 Module Data Width (continued) 0 00 00 00 8 Module Interface Levels LVTTL 01 01 01 9 SDRAM Cycle Time at CL=3 7.5 ns 75 75 A0 10 SDRAM Access Time from Clock at CL=3 5.4 ns 54 54 60 11 Dimm Config (Error Det/Corr.) ECC 02 02 02 12 Refresh Rate/Type Self-Refresh, 15.6 µs80 80 80 13 SDRAM width, Primary x8 08 08 08 14 Error Checking SDRAM Data Width n/a / x8 08 08 08 15 Minimum Clock Delay from Back to Back Random Column Address tccd =1CLK 01 01 01 16 Burst Length Supported 1, 2, 4, 8 0F 0F 0F 17 Number of SDRAM Banks 4 04 04 04 18 Supported CAS Latencies CL = 3 06 06 06 19 CS Latencies CS Latency = 0 01 01 01 20 WE Latencies WL = 0 01 01 01 21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00 22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E 23 Minimum Clock Cycle Time at CAS Latency =2 Not Supported 75 A0 A0 24 Maximum Data Access Time from Clock for CL = 2 Not Supported 54 60 60 25 MinimumClock CycleTimeat CL=1 Not Supported 00 00 00 26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00 00 00 27 Minimum Row Precharge Time 20 ns 0F 14 14 |
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