EM610FV8 datasheet(6/11 Pages) EMLSI | 128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM

Part Name

Description

EM610FV8

128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM ( 11 Page)

EMLSI

6 page

EM610FV8 Series

Low Power, 128Kx8 SRAM

merging Memory & Logic Solutions Inc.

tRC

Address

CS1

CS2

Data Out

tCO

tOH

High-Z

OHZ

TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)

Data Valid

OLZ

tAA

tHZ

tRC

Address

tAA

Data Valid

tOH

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=V

IL, CS2= WE=V IH )

Data Out

TIMING DIAGRAMS

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

1 2 3 4 5 6 7 8 9 10 11

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