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M2006-02A-622.0800 Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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M2006-02A-622.0800 Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 8 page M2006-02A Datasheet Rev 1.0 7 of 8 Revised 28Jul2004 Integr ated Circuit Systems , Inc. ● Ne tw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (508 ) 85 2-54 00 M2006-02A VCSO BASED FEC CLOCK PLL Prod uct Data Sh eet Integrated Circuit Systems, Inc. ELECTRICAL SPECIFICATIONS (CONTINUED) PARAMETER MEASUREMENT INFORMATION Output Rise and Fall Time Figure 5: Output Rise and Fall Time Output Duty Cycle Figure 6: Output Duty Cycle AC Characteristics Unless stated otherwise, V CC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), T A = -40 oC to +85 oC (industrial), F VCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50 Ω to V CC - 2V Symbol Parameter Min Typ Max Unit Test Conditions Input Frequency Range F IN Input Frequency DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 10 700 MHz Output Frequency F FOUT Output Frequency Range FOUT0, nFOUT0, FOUT1, nFOUT1 100 700 MHz APR VCSO Pull-Range Commercial ±120 ±200 ppm Industrial ±50 ±150 ppm PLL Loop Constants 1 Note 1: Parameters needed for PLL Simulator software; see Table 8, Example External Loop Filter Component Values, on pg. 5. K VCO VCO Gain 800 kHz/V R IN Internal Loop Resistor 50 k Ω BW VCSO VCSO Bandwidth 700 kHz Phase Noise and Jitter Φn Single Side Band Phase Noise @622.08MHz 1 kHz Offset -73 dBc/Hz Fin=19.44 MHz Mfin=32, Mfec=1, Rfec=1 10 kHz Offset -103 dBc/Hz 100 kHz Offset -126 dBc/Hz J(t) Jitter (rms) @622.08MHz 12kHz to 20MHz 0.25 0.5 ps rms 50kHz to 80MHz 0.25 0.5 ps rms t PW Output Duty Cycle 2 FOUT0, nFOUT0, FOUT1, nFOUT1 Note 2: See Parameter Measurement Information on pg. 7. P0, P1 = 1 40 50 60 % P0, P1 = 4 45 50 55 % t R Output Rise Time 2 FOUT0, nFOUT0, FOUT1, nFOUT1 200 450 500 ps 20 % to 80% t F Output Fall Time 2 200 450 500 ps 20 % to 80% Table 12: AC Characteristics 20% 80% tR 20% tF 80% Clock Output V P -P nFOUT FOUT t PW t PERIOD (Output Pulse Width) tPERIOD tPW odc = |
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