List of Tables
Table 1.
Documentation Conventions ............................................................................................ 18
Table 3-1.
Memory Map ................................................................................................................... 39
Table 4-1.
Exception Types .............................................................................................................. 41
Table 4-2.
Interrupts ........................................................................................................................ 42
Table 5-1.
JTAG Port Pins Reset State ............................................................................................. 46
Table 5-2.
JTAG Instruction Register Commands ............................................................................... 51
Table 6-1.
System Control Register Map ........................................................................................... 61
Table 7-1.
Hibernation Module Register Map ................................................................................... 121
Table 8-1.
Flash Protection Policy Combinations ............................................................................. 137
Table 8-2.
Flash Resident Registers ............................................................................................... 138
Table 8-3.
Flash Register Map ........................................................................................................ 138
Table 9-1.
GPIO Pad Configuration Examples ................................................................................. 162
Table 9-2.
GPIO Interrupt Configuration Example ............................................................................ 162
Table 9-3.
GPIO Register Map ....................................................................................................... 164
Table 10-1.
16-Bit Timer With Prescaler Configurations ..................................................................... 204
Table 10-2.
Timers Register Map ...................................................................................................... 210
Table 11-1.
Watchdog Timer Register Map ........................................................................................ 237
Table 12-1.
Samples and FIFO Depth of Sequencers ........................................................................ 260
Table 12-2.
ADC Register Map ......................................................................................................... 264
Table 13-1.
UART Register Map ....................................................................................................... 298
Table 14-1.
SSI Register Map .......................................................................................................... 343
Table 15-1.
Examples of I2C Master Timer Period versus Speed Mode ............................................... 373
Table 15-2.
Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 382
Table 15-3.
Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 387
Table 16-1.
TX & RX FIFO Organization ........................................................................................... 409
Table 16-2.
Ethernet Register Map ................................................................................................... 412
Table 17-1.
Comparator 0 Operating Modes ..................................................................................... 451
Table 17-2.
Comparator 1 Operating Modes ..................................................................................... 451
Table 17-3.
Comparator 2 Operating Modes ...................................................................................... 452
Table 17-4.
Internal Reference Voltage and ACREFCTL Field Values ................................................. 452
Table 17-5.
Analog Comparators Register Map ................................................................................. 454
Table 19-1.
Signals by Pin Number ................................................................................................... 463
Table 19-2.
Signals by Signal Name ................................................................................................. 467
Table 19-3.
Signals by Function, Except for GPIO ............................................................................. 471
Table 19-4.
GPIO Pins and Alternate Functions ................................................................................. 474
Table 20-1.
Temperature Characteristics ........................................................................................... 476
Table 20-2.
Thermal Characteristics ................................................................................................. 476
Table 21-1.
Maximum Ratings .......................................................................................................... 477
Table 21-2.
Recommended DC Operating Conditions ........................................................................ 477
Table 21-3.
LDO Regulator Characteristics ....................................................................................... 478
Table 21-4.
Detailed Power Specifications ........................................................................................ 479
Table 21-5.
Flash Memory Characteristics ........................................................................................ 480
Table 21-6.
Phase Locked Loop (PLL) Characteristics ....................................................................... 480
Table 21-7.
Clock Characteristics ..................................................................................................... 480
Table 21-8.
Crystal Characteristics ................................................................................................... 481
Table 21-9.
ADC Characteristics ....................................................................................................... 481
October 08, 2007
10
Preliminary
Table of Contents