14
Synchronous Serial Interface (SSI) ................................................................................ 329
14.1
Block Diagram ........................................................................................................................ 329
14.2
Functional Description ............................................................................................................. 329
14.2.1 Bit Rate Generation ................................................................................................................. 330
14.2.2 FIFO Operation ....................................................................................................................... 330
14.2.3 Interrupts ................................................................................................................................ 330
14.2.4 Frame Formats ....................................................................................................................... 331
14.3
Initialization and Configuration ................................................................................................. 338
14.4
Register Map .......................................................................................................................... 339
14.5
Register Descriptions .............................................................................................................. 340
15
Inter-Integrated Circuit (I2C) Interface ............................................................................ 366
15.1
Block Diagram ........................................................................................................................ 366
15.2
Functional Description ............................................................................................................. 366
15.2.1 I2C Bus Functional Overview .................................................................................................... 367
15.2.2 Available Speed Modes ........................................................................................................... 369
15.2.3 Interrupts ................................................................................................................................ 370
15.2.4 Loopback Operation ................................................................................................................ 370
15.2.5 Command Sequence Flow Charts ............................................................................................ 371
15.3
Initialization and Configuration ................................................................................................. 377
15.4
I2C Register Map ..................................................................................................................... 378
15.5
Register Descriptions (I2C Master) ........................................................................................... 379
15.6
Register Descriptions (I2C Slave) ............................................................................................. 392
16
Ethernet Controller .......................................................................................................... 401
16.1
Block Diagram ........................................................................................................................ 402
16.2
Functional Description ............................................................................................................. 402
16.2.1 Internal MII Operation .............................................................................................................. 402
16.2.2 PHY Configuration/Operation ................................................................................................... 403
16.2.3 MAC Configuration/Operation .................................................................................................. 404
16.2.4 Interrupts ................................................................................................................................ 406
16.3
Initialization and Configuration ................................................................................................. 407
16.4
Ethernet Register Map ............................................................................................................. 407
16.5
Ethernet MAC Register Descriptions ......................................................................................... 409
16.6
MII Management Register Descriptions ..................................................................................... 426
17
Pulse Width Modulator (PWM) ........................................................................................ 445
17.1
Block Diagram ........................................................................................................................ 445
17.2
Functional Description ............................................................................................................. 445
17.2.1 PWM Timer ............................................................................................................................. 445
17.2.2 PWM Comparators .................................................................................................................. 446
17.2.3 PWM Signal Generator ............................................................................................................ 447
17.2.4 Dead-Band Generator ............................................................................................................. 448
17.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 448
17.2.6 Synchronization Methods ......................................................................................................... 448
17.2.7 Fault Conditions ...................................................................................................................... 449
17.2.8 Output Control Block ............................................................................................................... 449
17.3
Initialization and Configuration ................................................................................................. 449
17.4
Register Map .......................................................................................................................... 450
17.5
Register Descriptions .............................................................................................................. 451
November 30, 2007
6
Preliminary
Table of Contents