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LM3S801-IRN20-A0T Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers

Part # LM3S801-IRN20-A0T
Description  Microcontroller
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LM3S801-IRN20-A0T Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers

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List of Figures
8
October 8, 2006
Preliminary
List of Figures
Figure 1-1.
Stellaris High-Level Block Diagram ........................................................................................... 27
Figure 1-2.
LM3S801 Controller System-Level Block Diagram ................................................................... 33
Figure 2-1.
CPU Block Diagram .................................................................................................................. 35
Figure 2-2.
TPIU Block Diagram .................................................................................................................. 36
Figure 5-1.
JTAG Module Block Diagram .................................................................................................... 43
Figure 5-2.
Test Access Port State Machine ............................................................................................... 46
Figure 5-3.
IDCODE Register Format.......................................................................................................... 50
Figure 5-4.
BYPASS Register Format ......................................................................................................... 50
Figure 5-5.
Boundary Scan Register Format ............................................................................................... 51
Figure 6-1.
External Circuitry to Extend Reset............................................................................................. 53
Figure 6-2.
Main Clock Tree ........................................................................................................................ 56
Figure 7-1.
Flash Block Diagram ................................................................................................................. 95
Figure 8-1.
GPIO Module Block Diagram .................................................................................................. 110
Figure 8-2.
GPIO Port Block Diagram........................................................................................................ 111
Figure 8-3.
GPIODATA Write Example...................................................................................................... 112
Figure 8-4.
GPIODATA Read Example ..................................................................................................... 112
Figure 9-1.
GPTM Module Block Diagram ................................................................................................. 148
Figure 9-2.
16-Bit Input Edge Count Mode Example ................................................................................. 152
Figure 9-3.
16-Bit Input Edge Time Mode Example...................................................................................153
Figure 9-4.
16-Bit PWM Mode Example .................................................................................................... 154
Figure 10-1.
WDT Module Block Diagram ................................................................................................... 179
Figure 11-1.
UART Module Block Diagram.................................................................................................. 203
Figure 11-2.
UART Character Frame........................................................................................................... 204
Figure 12-1.
SSI Module Block Diagram...................................................................................................... 238
Figure 12-2.
TI Synchronous Serial Frame Format (Single Transfer).......................................................... 240
Figure 12-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 241
Figure 12-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 242
Figure 12-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 242
Figure 12-6.
Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 243
Figure 12-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 243
Figure 12-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 244
Figure 12-9.
Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 244
Figure 12-10. MICROWIRE Frame Format (Single Frame)........................................................................... 245
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................................... 246
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements............................ 247
Figure 13-1.
I2C Block Diagram ................................................................................................................... 273
Figure 13-2.
I2C Bus Configuration.............................................................................................................. 274
Figure 13-3.
Data Validity During Bit Transfer on the I2C Bus..................................................................... 274
Figure 13-4.
START and STOP Conditions ................................................................................................. 274
Figure 13-5.
Complete Data Transfer with a 7-Bit Address ......................................................................... 275
Figure 13-6.
R/S Bit in First Byte ................................................................................................................. 276
Figure 13-7.
Master Single SEND................................................................................................................ 276
Figure 13-8.
Master Single RECEIVE.......................................................................................................... 277
Figure 13-9.
Master Burst SEND ................................................................................................................. 278
Figure 13-10. Master Burst RECEIVE ........................................................................................................... 279
Figure 13-11. Master Burst RECEIVE after Burst SEND...............................................................................280


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