LM3S617 Data Sheet
May 4, 2007
5
Preliminary
10.4
Register Map ..................................................................................................................................... 185
10.5
Register Descriptions......................................................................................................................... 186
11.
Analog-to-Digital Converter (ADC) .................................................................................. 207
11.1
Block Diagram ................................................................................................................................... 208
11.2
Functional Description ....................................................................................................................... 208
11.2.1 Sample Sequencers .......................................................................................................................... 208
11.2.2 Module Control .................................................................................................................................. 209
11.2.3 Hardware Sample Averaging Circuit.................................................................................................. 210
11.2.4 Analog-to-Digital Converter ............................................................................................................... 210
11.2.5 Test Modes ........................................................................................................................................ 210
11.2.6 Internal Temperature Sensor............................................................................................................. 210
11.3
Initialization and Configuration........................................................................................................... 210
11.3.1 Module Initialization ........................................................................................................................... 211
11.3.2 Sample Sequencer Configuration...................................................................................................... 211
11.4
Register Map ..................................................................................................................................... 211
11.5
Register Descriptions......................................................................................................................... 212
12.
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 237
12.1
Block Diagram ................................................................................................................................... 238
12.2
Functional Description ....................................................................................................................... 238
12.2.1 Transmit/Receive Logic ..................................................................................................................... 238
12.2.2 Baud-Rate Generation....................................................................................................................... 239
12.2.3 Data Transmission............................................................................................................................. 240
12.2.4 FIFO Operation .................................................................................................................................. 240
12.2.5 Interrupts............................................................................................................................................ 240
12.2.6 Loopback Operation .......................................................................................................................... 241
12.3
Initialization and Configuration........................................................................................................... 241
12.4
Register Map ..................................................................................................................................... 242
12.5
Register Descriptions......................................................................................................................... 243
13.
Synchronous Serial Interface (SSI) ................................................................................. 273
13.1
Block Diagram ................................................................................................................................... 273
13.2
Functional Description ....................................................................................................................... 274
13.2.1 Bit Rate Generation ........................................................................................................................... 274
13.2.2 FIFO Operation .................................................................................................................................. 274
13.2.3 Interrupts............................................................................................................................................ 274
13.2.4 Frame Formats .................................................................................................................................. 275
13.3
Initialization and Configuration........................................................................................................... 282
13.4
Register Map ..................................................................................................................................... 283
13.5
Register Descriptions......................................................................................................................... 284
14.
Analog Comparator........................................................................................................... 308
14.1
Block Diagram ................................................................................................................................... 308
14.2
Functional Description ....................................................................................................................... 308
14.2.1 Internal Reference Programming....................................................................................................... 309
14.3
Initialization and Configuration........................................................................................................... 310
14.4
Register Map ..................................................................................................................................... 311
14.5
Register Descriptions......................................................................................................................... 311
15.
Pulse Width Modulator (PWM) ......................................................................................... 319
15.1
Block Diagram ................................................................................................................................... 319
15.2
Functional Description ....................................................................................................................... 319