Figure 13-13. Slave Command Sequence ............................................................................................ 302
Figure 14-1.
Analog Comparator Module Block Diagram ..................................................................... 327
Figure 14-2.
Structure of Comparator Unit .......................................................................................... 328
Figure 14-3.
Comparator Internal Reference Structure ........................................................................ 329
Figure 15-1.
Pin Connection Diagram ................................................................................................ 339
Figure 18-1.
Load Conditions ............................................................................................................ 350
Figure 18-2.
I2C Timing ..................................................................................................................... 352
Figure 18-3.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 352
Figure 18-4.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 353
Figure 18-5.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 353
Figure 18-6.
JTAG Test Clock Input Timing ......................................................................................... 354
Figure 18-7.
JTAG Test Access Port (TAP) Timing .............................................................................. 355
Figure 18-8.
JTAG TRST Timing ........................................................................................................ 355
Figure 18-9.
External Reset Timing (RST) .......................................................................................... 356
Figure 18-10. Power-On Reset Timing ................................................................................................. 356
Figure 18-11. Brown-Out Reset Timing ................................................................................................ 357
Figure 18-12. Software Reset Timing ................................................................................................... 357
Figure 18-13. Watchdog Reset Timing ................................................................................................. 357
Figure 18-14. LDO Reset Timing ......................................................................................................... 357
Figure 19-1.
48-Pin LQFP Package ................................................................................................... 358
October 01, 2007
8
Preliminary
Table of Contents