6.1.3
Power Control ........................................................................................................................... 56
6.1.4
Clock Control ............................................................................................................................ 56
6.1.5
System Control ......................................................................................................................... 58
6.2
Initialization and Configuration ................................................................................................... 59
6.3
Register Map ............................................................................................................................ 59
6.4
Register Descriptions ................................................................................................................ 60
7
Hibernation Module .......................................................................................................... 110
7.1
Block Diagram ........................................................................................................................ 111
7.2
Functional Description ............................................................................................................. 111
7.2.1
Register Access Timing ........................................................................................................... 111
7.2.2
Clock Source .......................................................................................................................... 112
7.2.3
Battery Management ............................................................................................................... 112
7.2.4
Real-Time Clock ...................................................................................................................... 112
7.2.5
Non-Volatile Memory ............................................................................................................... 113
7.2.6
Power Control ......................................................................................................................... 113
7.2.7
Interrupts and Status ............................................................................................................... 113
7.3
Initialization and Configuration ................................................................................................. 114
7.3.1
Initialization ............................................................................................................................. 114
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 114
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 114
7.3.4
External Wake-Up from Hibernation .......................................................................................... 115
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 115
7.4
Register Map .......................................................................................................................... 115
7.5
Register Descriptions .............................................................................................................. 116
8
Internal Memory ............................................................................................................... 129
8.1
Block Diagram ........................................................................................................................ 129
8.2
Functional Description ............................................................................................................. 129
8.2.1
SRAM Memory ........................................................................................................................ 129
8.2.2
Flash Memory ......................................................................................................................... 130
8.3
Flash Memory Initialization and Configuration ........................................................................... 131
8.3.1
Flash Programming ................................................................................................................. 131
8.3.2
Nonvolatile Register Programming ........................................................................................... 132
8.4
Register Map .......................................................................................................................... 132
8.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 133
8.6
Flash Register Descriptions (System Control Offset) .................................................................. 140
9
General-Purpose Input/Outputs (GPIOs) ....................................................................... 153
9.1
Functional Description ............................................................................................................. 153
9.1.1
Data Control ........................................................................................................................... 153
9.1.2
Interrupt Control ...................................................................................................................... 154
9.1.3
Mode Control .......................................................................................................................... 155
9.1.4
Commit Control ....................................................................................................................... 155
9.1.5
Pad Control ............................................................................................................................. 155
9.1.6
Identification ........................................................................................................................... 155
9.2
Initialization and Configuration ................................................................................................. 155
9.3
Register Map .......................................................................................................................... 157
9.4
Register Descriptions .............................................................................................................. 158
October 09, 2007
4
Preliminary
Table of Contents