Figure 13-11. Master Burst RECEIVE after Burst SEND ........................................................................ 311
Figure 13-12. Master Burst SEND after Burst RECEIVE ........................................................................ 312
Figure 13-13. Slave Command Sequence ............................................................................................ 313
Figure 14-1.
Analog Comparator Module Block Diagram ..................................................................... 338
Figure 14-2.
Structure of Comparator Unit .......................................................................................... 339
Figure 14-3.
Comparator Internal Reference Structure ........................................................................ 340
Figure 15-1.
PWM Module Block Diagram .......................................................................................... 350
Figure 15-2.
PWM Count-Down Mode ................................................................................................ 351
Figure 15-3.
PWM Count-Up/Down Mode .......................................................................................... 352
Figure 15-4.
PWM Generation Example In Count-Up/Down Mode ....................................................... 352
Figure 15-5.
PWM Dead-Band Generator ........................................................................................... 353
Figure 16-1.
QEI Block Diagram ........................................................................................................ 386
Figure 16-2.
Quadrature Encoder and Velocity Predivider Operation .................................................... 388
Figure 17-1.
Pin Connection Diagram ................................................................................................ 403
Figure 20-1.
Load Conditions ............................................................................................................ 415
Figure 20-2.
I2C Timing ..................................................................................................................... 417
Figure 20-3.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 417
Figure 20-4.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 418
Figure 20-5.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 418
Figure 20-6.
JTAG Test Clock Input Timing ......................................................................................... 419
Figure 20-7.
JTAG Test Access Port (TAP) Timing .............................................................................. 420
Figure 20-8.
JTAG TRST Timing ........................................................................................................ 420
Figure 20-9.
External Reset Timing (RST) .......................................................................................... 421
Figure 20-10. Power-On Reset Timing ................................................................................................. 421
Figure 20-11. Brown-Out Reset Timing ................................................................................................ 422
Figure 20-12. Software Reset Timing ................................................................................................... 422
Figure 20-13. Watchdog Reset Timing ................................................................................................. 422
Figure 20-14. LDO Reset Timing ......................................................................................................... 422
Figure 21-1.
48-Pin LQFP Package ................................................................................................... 423
9
October 01, 2007
Preliminary
LM3S601 Microcontroller
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