6.1.3
Power Control ........................................................................................................................... 58
6.1.4
Clock Control ............................................................................................................................ 58
6.1.5
System Control ......................................................................................................................... 60
6.2
Initialization and Configuration ................................................................................................... 61
6.3
Register Map ............................................................................................................................ 61
6.4
Register Descriptions ................................................................................................................ 62
7
Hibernation Module .......................................................................................................... 113
7.1
Block Diagram ........................................................................................................................ 114
7.2
Functional Description ............................................................................................................. 114
7.2.1
Register Access Timing ........................................................................................................... 114
7.2.2
Clock Source .......................................................................................................................... 115
7.2.3
Battery Management ............................................................................................................... 115
7.2.4
Real-Time Clock ...................................................................................................................... 115
7.2.5
Non-Volatile Memory ............................................................................................................... 116
7.2.6
Power Control ......................................................................................................................... 116
7.2.7
Interrupts and Status ............................................................................................................... 116
7.3
Initialization and Configuration ................................................................................................. 117
7.3.1
Initialization ............................................................................................................................. 117
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 117
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 117
7.3.4
External Wake-Up from Hibernation .......................................................................................... 118
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 118
7.4
Register Map .......................................................................................................................... 118
7.5
Register Descriptions .............................................................................................................. 119
8
Internal Memory ............................................................................................................... 132
8.1
Block Diagram ........................................................................................................................ 132
8.2
Functional Description ............................................................................................................. 132
8.2.1
SRAM Memory ........................................................................................................................ 132
8.2.2
Flash Memory ......................................................................................................................... 133
8.3
Flash Memory Initialization and Configuration ........................................................................... 134
8.3.1
Flash Programming ................................................................................................................. 134
8.3.2
Nonvolatile Register Programming ........................................................................................... 135
8.4
Register Map .......................................................................................................................... 135
8.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 136
8.6
Flash Register Descriptions (System Control Offset) .................................................................. 143
9
General-Purpose Input/Outputs (GPIOs) ....................................................................... 156
9.1
Functional Description ............................................................................................................. 156
9.1.1
Data Control ........................................................................................................................... 157
9.1.2
Interrupt Control ...................................................................................................................... 158
9.1.3
Mode Control .......................................................................................................................... 159
9.1.4
Commit Control ....................................................................................................................... 159
9.1.5
Pad Control ............................................................................................................................. 159
9.1.6
Identification ........................................................................................................................... 159
9.2
Initialization and Configuration ................................................................................................. 159
9.3
Register Map .......................................................................................................................... 160
9.4
Register Descriptions .............................................................................................................. 162
November 30, 2007
4
Preliminary
Table of Contents