List of Tables
Table 1.
Documentation Conventions ............................................................................................ 21
Table 3-1.
Memory Map ................................................................................................................... 43
Table 4-1.
Exception Types .............................................................................................................. 45
Table 4-2.
Interrupts ........................................................................................................................ 46
Table 5-1.
JTAG Port Pins Reset State ............................................................................................. 50
Table 5-2.
JTAG Instruction Register Commands ............................................................................... 55
Table 6-1.
System Control Register Map ........................................................................................... 65
Table 7-1.
Hibernation Module Register Map ................................................................................... 122
Table 8-1.
Flash Protection Policy Combinations ............................................................................. 138
Table 8-2.
Flash Resident Registers ............................................................................................... 139
Table 8-3.
Flash Register Map ........................................................................................................ 139
Table 9-1.
GPIO Pad Configuration Examples ................................................................................. 163
Table 9-2.
GPIO Interrupt Configuration Example ............................................................................ 163
Table 9-3.
GPIO Register Map ....................................................................................................... 165
Table 10-1.
16-Bit Timer With Prescaler Configurations ..................................................................... 205
Table 10-2.
Timers Register Map ...................................................................................................... 211
Table 11-1.
Watchdog Timer Register Map ........................................................................................ 238
Table 12-1.
Samples and FIFO Depth of Sequencers ........................................................................ 261
Table 12-2.
ADC Register Map ......................................................................................................... 265
Table 13-1.
UART Register Map ....................................................................................................... 299
Table 14-1.
SSI Register Map .......................................................................................................... 344
Table 15-1.
Transmit Message Object Bit Settings ............................................................................. 375
Table 15-2.
Receive Message Object Bit Settings .............................................................................. 377
Table 15-3.
CAN Protocol Ranges .................................................................................................... 379
Table 15-4.
CAN Register Map ......................................................................................................... 382
Table 16-1.
TX & RX FIFO Organization ........................................................................................... 416
Table 16-2.
Ethernet Register Map ................................................................................................... 419
Table 17-1.
Comparator 0 Operating Modes ...................................................................................... 457
Table 17-2.
Internal Reference Voltage and ACREFCTL Field Values ................................................. 458
Table 17-3.
Analog Comparators Register Map ................................................................................. 459
Table 18-1.
PWM Register Map ........................................................................................................ 472
Table 19-1.
QEI Register Map .......................................................................................................... 506
Table 21-1.
Signals by Pin Number ................................................................................................... 521
Table 21-2.
Signals by Signal Name ................................................................................................. 525
Table 21-3.
Signals by Function, Except for GPIO ............................................................................. 529
Table 21-4.
GPIO Pins and Alternate Functions ................................................................................. 532
Table 22-1.
Temperature Characteristics ........................................................................................... 534
Table 22-2.
Thermal Characteristics ................................................................................................. 534
Table 23-1.
Maximum Ratings .......................................................................................................... 535
Table 23-2.
Recommended DC Operating Conditions ........................................................................ 535
Table 23-3.
LDO Regulator Characteristics ....................................................................................... 536
Table 23-4.
Detailed Power Specifications ........................................................................................ 537
Table 23-5.
Flash Memory Characteristics ........................................................................................ 538
Table 23-6.
Phase Locked Loop (PLL) Characteristics ....................................................................... 538
Table 23-7.
Clock Characteristics ..................................................................................................... 538
Table 23-8.
Crystal Characteristics ................................................................................................... 539
11
October 01, 2007
Preliminary
LM3S8971 Microcontroller