LM3S801 Data Sheet
October 8, 2006
9
Preliminary
Figure 13-12. Master Burst SEND after Burst RECEIVE...............................................................................280
Figure 13-13. Slave Command Sequence..................................................................................................... 281
Figure 14-1.
Analog Comparator Module Block Diagram ............................................................................ 305
Figure 14-2.
Structure of Comparator Unit................................................................................................... 306
Figure 14-3.
Comparator Internal Reference Structure ............................................................................... 307
Figure 15-1.
PWM Module Block Diagram................................................................................................... 317
Figure 15-2.
PWM Count-Down Mode......................................................................................................... 318
Figure 15-3.
PWM Count-Up/Down Mode ................................................................................................... 319
Figure 15-4.
PWM Generation Example In Count-Up/Down Mode ............................................................. 319
Figure 15-5.
PWM Dead-Band Generator ................................................................................................... 320
Figure 16-1.
QEI Block Diagram .................................................................................................................. 349
Figure 16-2.
Quadrature Encoder and Velocity Predivider Operation ......................................................... 350
Figure 17-1.
Pin Connection Diagram.......................................................................................................... 365
Figure 20-1.
Load Conditions....................................................................................................................... 381
Figure 20-2.
I2C Timing................................................................................................................................ 383
Figure 20-3.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 384
Figure 20-4.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 385
Figure 20-5.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 385
Figure 20-6.
JTAG Test Clock Input Timing................................................................................................. 387
Figure 20-7.
JTAG Test Access Port (TAP) Timing ..................................................................................... 387
Figure 20-8.
JTAG TRST Timing ................................................................................................................. 387
Figure 20-9.
External Reset Timing (RST)................................................................................................... 389
Figure 20-10. Power-On Reset Timing .......................................................................................................... 389
Figure 20-11. Brown-Out Reset Timing ......................................................................................................... 389
Figure 20-12. Software Reset Timing ............................................................................................................ 389
Figure 20-13. Watchdog Reset Timing .......................................................................................................... 390
Figure 20-14. LDO Reset Timing ................................................................................................................... 390
Figure 21-1.
48-Pin LQFP Package............................................................................................................. 391