Figure 15-9.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 436
Figure 15-10. MICROWIRE Frame Format (Single Frame) .................................................................... 437
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 438
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 438
Figure 16-1.
I2C Block Diagram ......................................................................................................... 468
Figure 16-2.
I2C Bus Configuration .................................................................................................... 469
Figure 16-3.
START and STOP Conditions ......................................................................................... 469
Figure 16-4.
Complete Data Transfer with a 7-Bit Address ................................................................... 470
Figure 16-5.
R/S Bit in First Byte ........................................................................................................ 470
Figure 16-6.
Data Validity During Bit Transfer on the I2C Bus ............................................................... 470
Figure 16-7.
Master Single SEND ...................................................................................................... 473
Figure 16-8.
Master Single RECEIVE ................................................................................................. 474
Figure 16-9.
Master Burst SEND ....................................................................................................... 475
Figure 16-10. Master Burst RECEIVE .................................................................................................. 476
Figure 16-11. Master Burst RECEIVE after Burst SEND ........................................................................ 477
Figure 16-12. Master Burst SEND after Burst RECEIVE ........................................................................ 478
Figure 16-13. Slave Command Sequence ............................................................................................ 479
Figure 17-1.
USB Module Block Diagram ........................................................................................... 503
Figure 18-1.
Analog Comparator Module Block Diagram ..................................................................... 591
Figure 18-2.
Structure of Comparator Unit .......................................................................................... 592
Figure 18-3.
Comparator Internal Reference Structure ........................................................................ 593
Figure 19-1.
PWM Unit Diagram ........................................................................................................ 603
Figure 19-2.
PWM Module Block Diagram .......................................................................................... 604
Figure 19-3.
PWM Count-Down Mode ................................................................................................ 605
Figure 19-4.
PWM Count-Up/Down Mode .......................................................................................... 605
Figure 19-5.
PWM Generation Example In Count-Up/Down Mode ....................................................... 606
Figure 19-6.
PWM Dead-Band Generator ........................................................................................... 606
Figure 20-1.
QEI Block Diagram ........................................................................................................ 657
Figure 20-2.
Quadrature Encoder and Velocity Predivider Operation .................................................... 659
Figure 21-1.
100-Pin LQFP Package Pin Diagram .............................................................................. 674
Figure 24-1.
Load Conditions ............................................................................................................ 694
Figure 24-2.
I2C Timing ..................................................................................................................... 697
Figure 24-3.
Hibernation Module Timing ............................................................................................. 698
Figure 24-4.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 698
Figure 24-5.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 699
Figure 24-6.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 699
Figure 24-7.
JTAG Test Clock Input Timing ......................................................................................... 700
Figure 24-8.
JTAG Test Access Port (TAP) Timing .............................................................................. 700
Figure 24-9.
External Reset Timing (RST) .......................................................................................... 701
Figure 24-10. Power-On Reset Timing ................................................................................................. 702
Figure 24-11. Brown-Out Reset Timing ................................................................................................ 702
Figure 24-12. Software Reset Timing ................................................................................................... 702
Figure 24-13. Watchdog Reset Timing ................................................................................................. 702
Figure 25-1.
100-Pin LQFP Package .................................................................................................. 703
April 08, 2008
10
Preliminary
Table of Contents