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Clock Timing
(GND = 0 V, Vcc = 4.5 to 5.5 V, Ta = -20 to + 75¢ J
)
Fig. 3
ns
150
--
--
tf
£ p1 - £ p2 fall time
Fig. 3
ns
150
--
--
tr
£ p1 - £ p2 rise time
Fig. 3
ns
--
--
625
tD21
£ p2 - £ p1 phase
difference
Fig. 3
ns
--
--
625
tD12
£ p1 - £ p2 phase
difference
Fig. 3
ns
--
--
1,875
tWH£ p2
£ p2 high level width
Fig. 3
ns
--
--
1,875
tWH£ p1
£ p1 high level width
Fig. 3
ns
--
--
625
tWL£ p2
£ p2 low level width
Fig. 3
ns
--
--
625
tWL£ p1
£ p1 low level width
Fig. 3
ns
20
--
2.5
tCYC
£ p1, £ p2 cycle time
Test Condition
Unit
Max
Typ
Min
Symbol
Item
Limit
Figure 3 External Clock Waveform
ASLIC MICROELECTRONICS CORP.
¸ à
µ Ø
¹ q¤ lª Ñ
¥ ÷
¦ ³
- -
¤ ½
¥ q
Page 9
tcyc
t
WH£p 1
tf
tr
0.7 Vcc
0.3 Vcc
t WL£p1
t D12
t D21
0.7 Vcc
0.3 Vcc
tf
t
tr
tcyc
t
WL£p 2
WH£p 2
£p1
£p2
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