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ST24C02RM3TR Datasheet(PDF) 8 Page - STMicroelectronics |
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ST24C02RM3TR Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 16 page SCL SDA SCL SDA SDA START CONDITION SDA INPUT SDA CHANGE AI00792 STOP CONDITION 1 23 7 89 MSB ACK START CONDITION SCL 1 23 7 89 MSB ACK STOP CONDITION Figure 6. I2C Bus Protocol Write Operations The Multibyte Write mode (only available on the ST24/25C02 and ST24C02R versions) is selected when the MODE pin is at VIH and the Page Write mode when MODE pin is at VIL. The MODE pin may be driven dynamically with CMOS input levels. Following a START condition the master sends a device select code with the RW bit reset to ’0’. The memory acknowledges this and waits for a byte address. The byte address of 8 bits provides ac- cess to 256 bytes of the memory. After receipt of the byte address the device again responds with an acknowledge. For the ST24/25W02 versions, any write command with WC = 1 will not modify the memory content. Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledged by the memory. The master then terminates the transfer by generating a STOP condition. The Write mode is independant of the state of the MODE pin which could be left floating if only this mode was to be used. However it is not a recommended operating mode, as this pin has to be connected to either VIH or VIL, to minimize the stand-by current. 8/16 ST24/25C02, ST24C02R, ST24/25W02 |
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