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ST52E301 Datasheet(PDF) 10 Page - STMicroelectronics |
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ST52E301 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 100 page Figure 2.5. Input Registers Bench description 2.2.2 Input Registers Bench The Input Registers (IR) bench consists of 11 8-bit registers co ntaining data or status of t he peripherals. All the registers can be specifiedby using a decimal address, e.g. 0 identifies the first register of the IR. The first four registers (ADC_OUT_0:3) of the IR are dedicated to the 4 converted values coming from the ADC. TMR_OUT registers contains the current counted value by the internal Timer; whereas TMR_ST is the Timer status. For details about TMR_ST, please refer to Timer description. Data read by the Parallel I/O Port are stored automatically in the 6-th register, INP_PORT. Data read by the SCI are stored automatically in the 7-th register SCI_IN and SCI status is stored in the SCI_ST register. For details about SCI_ST, please refer to SCI description. The Fuzzy Core writes the computed output values in the FUZZY_OUT_0:1 registers. 10/99 ST52T301/E301 |
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