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TMS320VC5509 Datasheet(PDF) 11 Page - Texas Instruments |
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TMS320VC5509 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 124 page  Features 11 April 2001 − Revised January 2008 SPRS163H 1 TMS320VC5509 Features D High-Performance, Low-Power, Fixed-Point TMS320C55x Digital Signal Processor − 6.94-ns Instruction Cycle Time for 144-MHz Clock Rate at 1.6 V − One/Two Instruction(s) Executed per Cycle − Dual Multipliers [Up to 288 Million Multiply-Accumulates per Second (MMACS)] − Two Arithmetic/Logic Units (ALUs) − Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses D 128K x 16-Bit On-Chip RAM, Composed of: − 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit − 192K Bytes of Single-Access RAM (SARAM) 24 Blocks of 4K × 16-Bit D 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit) D 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM) D 16-Bit External Parallel Bus Memory Supporting Either: − External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to: − Asynchronous Static RAM (SRAM) − Asynchronous EPROM − Synchronous DRAM (SDRAM) − 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities D Programmable Low-Power Control of Six Device Functional Domains D On-Chip Scan-Based Emulation Logic D On-Chip Peripherals − Two 20-Bit Timers − Watchdog Timer − Six-Channel Direct Memory Access (DMA) Controller − Three Serial Ports Supporting a Combination of: − Up to 3 Multichannel Buffered Serial Ports (McBSPs) − Up to 2 MultiMedia/Secure Digital Card Interfaces − Programmable Digital Phase-Locked Loop (DPLL) Clock Generator − Seven (LQFP) or Eight (BGA) General- Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF) − USB Full-Speed (12 Mbps) Slave Port Supporting Bulk, Interrupt and Isochronous Transfers − Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface − Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply − 4-Channel (BGA) or 2-Channel (LQFP) 10-Bit Successive Approximation A/D D IEEE Std 1149.1† (JTAG) Boundary Scan Logic D Packages: − 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix) − 179-Terminal MicroStar BGA (Ball Grid Array) (GHH Suffix) D 2.7-V – 3.6-V I/O Supply Voltage D 1.6-V Core Supply Voltage All trademarks are the property of their respective owners. TMS320C55x and MicroStar BGA are trademarks of Texas Instruments. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. |
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