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TAS5414A, TAS5424A

SLOS535A – JULY 2007 – REVISED FEBRUARY 2008

Table 1. TERMINAL FUNCTIONS

TERMINAL

DKD Package

PHD Package

DESCRIPTION

NAME

TAS5414A

TAS5424A

TAS5414A

TAS5424A

NO.

NO.

NO.

NO.

A_BYP

13

14

11

11

PBY

Bypass capacitor for the AVDD analog regulator

Open-drain CLIP, OTW, or logical OR of the CLIP and

CLIP_OTW

9

10

6

6

DO

OTW outputs. It also reports tweeter detection during

tweeter mode.

Top of main storage capacitor for charge pump (bottom

CP

28

34

41

41

CP

goes to PVDD)

CPC_BOT

27

33

40

40

CP

Bottom of flying capacitor for charge pump

CPC_TOP

29

35

42

42

CP

Top of flying capacitor for charge pump

D_BYP

8

9

5

5

PBY

Bypass pin for DVDD regulator output

Global fault output (open drain): UV, OV, OTSD, OCSD,

FAULT

5

5

1

1

DO

DC

3, 7, 8, 12,

3, 7, 8, 12,

14, 16, 17,

14, 16, 17,

21, 22, 23,

21, 22, 23,

GND

10

7, 11

DG

Ground

24, 25, 26,

24, 25, 26,

55, 56, 57,

55, 56, 57,

58, 59, 60

58, 59, 60

I2C_ADDR

2

2

62

62

AI

IN1_M

N/A

16

N/A

14

AI

Inverting analog input for channel 1 (TAS5424A only)

IN1_P

14

15

13

13

AI

Non-inverting analog input for channel 1

IN2_M

N/A

18

N/A

16

AI

Inverting analog input for channel 2 (TAS5424A only)

IN2_P

15

17

15

15

AI

Non-inverting analog input for channel 2

IN3_M

N/A

20

N/A

18

AI

Inverting analog input for channel 3 (TAS5424A only)

IN3_P

17

19

19

17

AI

Non-inverting analog input for channel 3

IN4_M

N/A

22

N/A

20

AI

Inverting analog input for channel 4 (TAS5424A only)

IN4_P

18

21

20

19

AI

Non-inverting analog input for channel 4

Signal return for the 4 analog channel inputs (TAS5414A

IN_M

16

N/A

18

N/A

ARTN

only)

MUTE

6

6

2

2

AI

Gain ramp control: mute (low), play (high)

Oscillator sync input from master or output to slave

OSC_SYNC

1

1

61

61

DI/DO

amplifiers (20 MHz divided by 5, 6, or 7)

OUT1_M

34

41

48

48

PO

– polarity output for bridge 1

OUT1_P

33

40

47

47

PO

+ polarity output for bridge 1

OUT2_M

31

37

45

45

PO

– polarity output for bridge 2

OUT2_P

30

36

44

44

PO

+ polarity output for bridge 2

OUT3_M

25

31

37

37

PO

– polarity output for bridge 3

OUT3_P

24

30

36

36

PO

+ polarity output for bridge 3

OUT4_M

22

27

34

34

PO

– polarity output for bridge 4

OUT4_P

21

26

33

33

PO

+ polarity output for bridge 4

30, 31, 32,

30, 31, 32,

28, 29, 32,

35, 38, 39,

35, 38, 39,

PGND

23, 26, 32

PGND

Power GND

38, 39

43, 46, 49,

43, 46, 49,

50, 51

50, 51

19, 20, 35,

23, 24, 25,

27, 28, 29,

27, 28, 29,

PVDD

PWR

PVDD supply

36

42, 43, 44

52, 53, 54

52, 53, 54

REXT

12

13

10

10

AI

Precision resistor pin to set clock frequency

SCL

4

4

64

64

DI

(1)

DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PGND = power ground,

PBY = power bypass, PO = power output, AG = analog ground, DG = digital ground, CP = charge pump.

Copyright © 2007–2008, Texas Instruments Incorporated

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Product Folder Link(s): TAS5414A TAS5424A