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ST70137TQFP Datasheet(PDF) 11 Page - STMicroelectronics |
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ST70137TQFP Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 22 page  ST70137 11/22 PCI_TRDYN I/O I L PCI Target Ready This signal is driven by the select target to indicate the tar- get is able to complete the current data phase. During read transactions, it indicates PCI_AD[] contains valid data. Wait states occur until both PCI_TRDYN and PCI_IRDYN are asserted togheter. PCI_PERRN I/O I L PCI Parity Error Only for reporting data parity errors for all bus transactions except for special cycles. It is driven by the agent receiving data two clock cycles after the parity was detected as an error. This signal is driven inactive (high) for one clock cycle prior to returning to the tri-state condition. PCI_SERRN O Z L PCI System Error Used to report address and data parity errors on special cycle commands and any other error condition having a catastrophic system impact. PCI_INTAN O Z L PCI Interrupt A This signal is defined as optional and level sensitive. Driv- ing it low will interrupt to the host. The PCI_INTAN inter- rupt is to be used for any single function device requiring an interrupt capability. PCI_PMEN O Z L PCI Power Management Event This signal is used to indicate that a power management event has been detected. The PCI_PMEN signal is asyn- chronous with respect to the PCI clock; it is set (if enabled) by the low to high transition of the ACTD signal. PCI_STOPN I/O I L PCI Stop This signal indicates the current target is requesting the master to stop the current transaction. USB INTERFACE DPLUS I/O I + Differential positive USB data input/output. DMINUS I/O I - Differential negative USB data input/output. MISCELLANEOUS INTERFACE GPIO[3: 0] I/O I - General Purpose I/O Bus These signals are controlled by internal registers located inside ADSL uP block. At the Power-up, Hardware or Software Reset the input direction is chosen. CFG_MEM_SEL I I - Select Internal [1] or External [0] PCI/USB configuration memory. USB_PCIN_sel I I - Select PCI [0] or USB [1] Interface Selecting USB interface and if all Test Pins are set to default value, all the PCI Pads are deactivated. The power supply for this section can be not provided. The PCI section is frozen. Selecting PCI interface the DMINUS and DPLUS has to be set to the low level (reset mode). The PLL is in power down and no any clock will be provided to the USB section. VAUX_D / USB_SP I I - VAUX Detect when USB_PCIN_sel = [0] or USB SELF POWERED when USB_PCIN_sel = [1]. Signal Name Direction Init Status Polarity Signal Description PIN DESCRIPTION (continued) |
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