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ST90R40C6 Datasheet(PDF) 11 Page - STMicroelectronics |
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ST90R40C6 Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 56 page  1.3.2.2 EEPROM Programming Procedure The programming of a byte of EEPROM memory is equivalent to writing a byte into a RAM location af- ter verifying that EEBUSY bit is low. Instructions operating on word data (16 bits) will not access the EEPROM. The EEPROM ENABLE bit EEWEN must first be set before writing to the EEPROM. When this bit is low, attempts to write data to the EEPROM have no affect, this prevents any spurious memory ac- cesses from affecting the data in the EEPROM. Termination of the write operation can be detected by polling on the EEBUSY status bit, or by inter- rupt, taking the interrupt vector from the External Interrupt 4 channel. The selection of the interrupt is made by EEPROM Interrupt enable bit EEIEN. It should be noted that the Mask bit of External Inter- rupt 4 should be set, and the Interrupt Pending bit reset, before the setting of EEIEN to prevent un- wanted interrupts. A delay (eg a nop instruction) should also be included between the operationson the mask and pending bits of External Interrupt 4. If polling on EEBUSY is used, a delay of 6 INTCLK clock cycles is necessary after the end of program- ming, this can be a nop instruction or, normally, therequired time to test the EEBUSY bit and to branch to the next instruction will be sufficient. While EEBUSY is active, any attempt to access the EEPROM matrix will be aborted and the data read will be invalid. EEBUSY is a read only bit and can- not be reset by the user if active. An erased bit of the EEPROM memory will read as a logic “0”, while a programmed cell will be read as a logic “1”. For applications requiring the highest level of reliability, the Verify Mode, set by EEPROM control register bit VRFY, allows the reading of the EEPROM memory cells with a reduced gate volt- age (typically 20%). If the EEPROM memory cell has been correctly programmed, a logic “1” will be read with the reduced voltage, otherwise a logic “0” will be read. 1.3.2.3 Parallel Programming Procedure Parallel programming is a feature of the EEPROM macrocell. One up to sixteen bytes of a same row can be programmed at once. The constraint is that each of the bytes occur in the same ROW of the EEPROM memory (A4 constant, A3-A0 variable). To operate this mode, the Parallel Mode enable bit, PLLEN, must be set. The data written is then latched into buffers (at the ad- dresses specified, which may be non-sequential) and then transferred to the EEPROM memory by the setting of the PLLST bit of the control register. Both PLLST and PLLEN are internally reset at the end of the programming cycle. Any attempt to read the EEPROM memory when PLLEN is set will give invalid data. In the event that the data in the buffer latches is not required to be written into the memory by the setting of PLLST, the correct way to terminate the operation is to reset PLLEN and to perform a dummy read of theEEPROMmemory. This termina- tion will clear all data present in the latches. 1.3.2.4 EEPROM Programming Voltage No external Vpp voltage is required, an internal 18Volt charge-pump gives the required energy by a dedicated oscillator pumping at a typical fre- quency of 5MHz, regardless of the external clock. 1.3.2.5 EEPROM Programming Time No timing routine is required to control the pro- gramming time as dedicated circuitry takes care of the EEPROM programming time (The typical pro- gramming time is 6ms). 1.3.2.6 EEPROM Interrupt Management At the end of each write procedure the EEPROM sends an interrupt request (if EEIEN bit is set). The EEPROM shares its interrupt channel with the ex- ternal interrupt source INT4, from which the priority level is derived. Care must be taken when EEIEN is reset. The as- sociated external interrupt channel must be dis- abled (by reseting bit 4 of EIMR, R244) along with reseting the interrupt pending bit (bit 4 of EIPR, R243) to prevent unwanted interrupts. A delay in- struction (at least 1 nop instruction) must be in- serted between these two operations WARNING. The content of the EEPROM of the ST9040 family after the out-going test at SGS- THOMSON’s manufacturing location is not guar- enteed. EEPROM (Continued) ® ST9040 11/56 |
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