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ST95022M3TR Datasheet(PDF) 5 Page - STMicroelectronics |
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ST95022M3TR Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 16 page AI01272 HOLD S W Control Logic High Voltage Generator I/O Shift Register Address Register and Counter Data Register 16 Bytes X Decoder Block Protect C D Q Status Figure 5. Block Diagram tected blocks. The blocks and respective WRSR control bits are shown in Table 4. When the WRSR instruction and the 8 bits of the Status Register are latched-in, the internal write cycle is then triggered by the rising edge of S. This rising edge of S must appear no later than the 16th clock cycle of the WRSR instruction of the Status Register content (it must not appear a 17th clock pulse before the rising edge of S), otherwise the internal write sequence is not performed. Status Register Bits Array Addresses Protected Protected Block BP1 BP0 0 0 none none 0 1 C0h - FFh Upper quarter 1 0 80h - FFh Upper half 1 1 00h - FFh Whole memory Table 4. Write Protected Block Size 5/16 ST95022 |
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