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ST95010WB1TR Datasheet(PDF) 3 Page - STMicroelectronics |
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ST95010WB1TR Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 18 page AI01438 C C MSB LSB CPHA Dor Q 0 1 CPOL 0 1 Figure 3. Data and Clock Timing AI01439B SPI Interface with (CPOL, CPHA) = (’0’, ’0’) or (’1’, ’1’) MICROCONTROLLER (ST6, ST7, ST9, ST10, OTHERS) ST95xx0 SCK SDI SDO C Q D Figure 4. Microcontroller and SPI Interface Set-up Serial Clock (C). The serial clock provides the timing of the serial interface. Instructions, ad- dresses, or data present at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes after the falling edge of the clock input. Chip Select (S). When S is high, the Memory is deselected and the Q output pin is at high imped- ance and, unless an internal write operation is underway the Memory will be in the standby power mode. S low enables the Memory, placing it in the active power mode. It should be noted that after power-on, a high to low transition on S is required prior to the start of any operation. Write Protect (W). This pin is for hardware write protection. When W is low, writes to the Memory are disabled but any other operationsstay enabled. When W is high, all writes operationsare available. W going low at any time before the last bit D0 of the data streamwill reset the write enable latch and prevent programming. No action on W or on the write enable latch can interrupt a write cycle which has commenced. 3/18 ST95040, ST95020, ST95010 |
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