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RMLD232UAW Datasheet(PDF) 8 Page - Emerging Memory & Logic Solutions Inc

Part # RMLD232UAW
Description  2M x 32 bit Low Power DDR SDRAM
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Manufacturer  EMLSI [Emerging Memory & Logic Solutions Inc]
Direct Link  http://www.emlsi.com
Logo EMLSI - Emerging Memory & Logic Solutions Inc

RMLD232UAW Datasheet(HTML) 8 Page - Emerging Memory & Logic Solutions Inc

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8
Rev 0.7
64Mb Low Power DDR SDRAM
Advanced
Extended Mode Register Set (EMRS)
The extended mode register is designed to support partial array self refresh or driver strength. EMRS cycle is not mandatory and the
EMRS command needs to be issued only when either PASR or DS is used. The defalt state without EMRS command issued is +85
,
all 4 banks refreshed and the half size of driver strength. The extended mode register is written by asserting low on CS, RAS,
CAS, WE and high on BA1, low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into
the extended mode register). The state of address pins A0 ~ A10 in the same cycle as CS, RAS, CAS and WE going low is written in
the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the
power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed
with the same command and four clock cycles. But this command must be issued only when all banks are in the idle state. A0 ~ A2
are used for partial array self refresh and A5 ~ A6 are used for driver strength. “High” on BA1 and “Low” on BA0 are used for EMRS.
All the other address pins except A0, A1, A2, A5, A6, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for
specific codes.
Extended MRS for PASR(Partial Array Self Refresh) & DS &
TCSR(Internal Temperature Compensated Self Refresh)
BA1
BA0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
0
0
0
0
0
DS
0
0
PASR
Driver Strength
A6
A5
Driver Strength
0
0
Full
0
1
1/2 (default)
1
0
1/4
1
1
1/8
Address Bus
Mode Register
Inernal TCSR
Self refresh cycle is controlled
automatically by internal tem-
perature sensor and control cir-
cuit according to the four
temperature ; Max 15
, Max
45
,
Max 70
,
Max 85
PASR
A2
A1
A0
Size of Refreshed
Array
0
0
0
Four Banks (default)
0
0
1
Two Banks
(Bank 0,1)
0
1
0
One Bank
(Bank 0)
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved


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