Advance Information

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com.

11

RMS132UAW

Table5: Command Truth Table

X

X

X

X

X

X

X

X

X

X

X

X

L/H

L/H

L/H

L/H

X

X

X

X

X

DQM

L

X

H

H

H

L

X

H

No Operation (NOP)

X

X

X

X

H

X

H

Command Inhinit (NOP)

V

V

V

L

H

H

H

L

H

H

H

L

H

H

H

L

X

X

H

L

Deep Power Down Exit

6

X

H

H

L

L

H

Deep Power Down Entry

X

X

H

L

Clock Suspend Exit

X

X

X

X

H

L

H

Clock Suspend Entry

X

X

X

X

H

H

L

Precharge Down Exit

X

X

X

X

H

L

H

Precharge Power Down Entry

2

X

X

X

X

H

H

L

Self Refresh Exit

3

X

H

L

L

L

L

H

Self Refresh Entry

3

X

H

L

L

L

H

H

Auto Refresh

X

L

H

H

L

H

H

Burst Stop

L

Bank

L

H

L

L

X

H

Precharge Selected Bank

H

X

L

H

L

L

X

H

Precharge All Banks

5

H

Bank/Col

L

L

H

L

X

H

Write with Autoprecharge

5

L

Bank/Col

L

L

H

L

X

H

Write

5

H

Bank/Col

H

L

H

L

X

H

Read with Autoprecharge

5

L

Bank/Col

H

L

H

L

X

H

Read

Bank/Row

H

H

L

L

X

H

Active (select bank and

activate row)

4

OP CODE

L

L

L

L

X

H

Extended Mode Register Set

4

OP CODE

L

L

L

L

X

H

Mode Register Set

Note

A10

ADDR

/WE

/CAS

/RAS

/CS

CKEn

CKEn-1

Function

Note :

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.

H: High Level, L: Low Level, X: Don't Care, V: Valid

2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once

tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum

of two NOP commands must be provided during tXSR period.

3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

4. A0-A10 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended

mode register set.

5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read

DQM Latency is 2 CLK.

6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is

assigned to the Deep Power Down function.