EM782SP16A

512Kx16 Multiplexed STRAM

6

TIMING DIAGRAMS

Device Operaton

The access is performed in two stages. The first stage is address latching. The first stage take place between point A and

B in timing diagram. At this stage, the Chip Select(CS) to the device is asserted. The random access is enabled either

from the point the address becomes stable, the falling edge of the AVD signal or from the falling edge of the last chip

select signal. The second stage is the read or write access. This takes place between points B and C in timing diagram.

tOE when it is dominant that the device gets into the read cycle since the address is available long before the device

output is enabled.

Read Access

low and the latch becomes transparent. This allows the address to be propagated to the memory array. The address is

stable at the rising edge of the AVD signal. The AVD signal goes high at point B in which the address latch is completed.

At this point the read cycle is entered. The OE signal is set active low. This changes the direction of the bus. The status

of control signals UB and LB are set according to the access. Data is read at point C.

Address Valid

Data Valid

C

B

A

AVD

OE

CS

UB, LB

Address/Data