EM782SP16A

512Kx16 Multiplexed STRAM

8

Write Access

low and the latch becomes transparent. This allows the address to be propagated to the memory array. The address is

stable at the rising edge of the AVD signal. The AVD signal goes high at point B in which the address latch is completed.

At this point, the second stage of the write process is entered. Data is input to the multiplexed address/data bus. The WE

signal is set low and control signal UB and LB are set according to the access.

Address Valid

Data Valid

C

B

A

AVD

WE

CS

UB, LB

Address/Data

Address Valid

Data Valid

C

B

A

AVD

WE

CS

UB, LB

Address/Data

NOTES (WRITE CYCLE)

low WE with asserting UB or LB low for single byte operation or simultaneously asserting UB and LB low for word operation. A write