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EMC646SP16JZ-45L Datasheet(PDF) 10 Page - Emerging Memory & Logic Solutions Inc

Part # EMC646SP16JZ-45L
Description  4Mx16 bit CellularRAM
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Manufacturer  EMLSI [Emerging Memory & Logic Solutions Inc]
Direct Link  http://www.emlsi.com
Logo EMLSI - Emerging Memory & Logic Solutions Inc

EMC646SP16JZ-45L Datasheet(HTML) 10 Page - Emerging Memory & Logic Solutions Inc

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EMC646SP16J
4Mx16 CellularRAM
10
Preliminary
Bus Operating Modes
64M CelluarRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This
bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined
by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode.This mode uses the industry- standard SRAM control bus (CE#,
OE#, WE#, and LB#/UB#). READ operations (Figure 3) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE#
HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 4) occur when
CE#, WE#, and LB#/UB# are driven LOW. During asychronous WRITE operations, the OE# level is a “Don’t care”, and WE# will over-
ride OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asychronous opera-
tions (page mode disabled) can either use the ADV# input to latch the address, or ADV# can be driven LOW during the entire READ/
WRITE operation.
During asychronous operation, the CLK input must be held static LOW. WAIT will be driven while the device is enabled and its state
should be ignored. WE# LOW time must be limited to tCEM
Figure 3: READ Operation (ADV# LOW)
Note: ADV# must remain Low for PAGE MODE operation.
High-Z
Don’t Care
CE#
Address
OE#
LB#/UB#
DATA
tRC = READ Cycle Time
Data Valid
Address Valid
WE#


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