EMP116MEAW Series

1Mx16 Pseudo Static RAM

Preliminary

Rev 0.0

LOW POWER MODES

Mode Register Set

DPD Enable / Disable

Array Mode Selection

Array Half Selection (Top/Down)

Array Refresh Area Selection

A19 ~ A5

A4

A3

A2

A1

A0

All 0

(Reserved for

future)

DPD

Enable/Disable

Array Mode

Selection

Array Half

Selection

Array Refresh Area Selection

A4

Type

A3

Type

0

Deep Power Down Enable

0

Partial Array Refresh Mode (Default)

1

DPD Disable (Default)

1

Reduced Memory Size Mode

A2

Type

A1

A0

Type

0

Bottom (Default)

0

0

Full Array (Default)

1

Top

0

1

RFU (Reserved for future)

1

0

1/2 Array

1

1

1/4 Array

NOTES

1. The Partial Array Refresh and Deep Power Down mode is issued only during ZZ# low state.

2. The RMS (Reduced Memory Size) mode is enabled after ZZ# goes high and remains enabled after ZZ# goes high. To

change to a different mode, the mode register will have to be re-written.

3. If register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that

ZZ# is driven low and there is no MRS update. When ZZ# is driven high, all of the register settings will return to dafault state

for the part (i.e. full array refresh, Deep Power Down disabled.)

Address

CS#

LB#,UB#

WE#

ZZ#

Mode Register Set UpdateTiming Diagram

NOTES

selected. The data bus is a don’t care when ZZ# is low during the register updates.

Register write start

Register write complete

Register update complete