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EMC326SP16AJU-90L Datasheet(PDF) 8 Page - Emerging Memory & Logic Solutions Inc |
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EMC326SP16AJU-90L Datasheet(HTML) 8 Page - Emerging Memory & Logic Solutions Inc |
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8 / 64 page  EMC326SP16AJ 2Mx16 CellularRAM 8 Preliminary Table 2: Bus Operations Note: 1. CLK must be LOW during async read and async write modes; and to achieve standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VccQ or 0V; all device pins must be static (unswitched) in order to achieve standby current. 7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transitions from HIGH to LOW. 8. When the BCR is configured for sync mode, sync READ and WRITE, and async WRITE are supported by EMLSI. 9. Burst mode operation is initialized through the bus configuration register (BCR[15]). 10. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated by WAIT). Asynchfonous Mode BCR[15]=1 Power CLK1 ADV# CE# OE# WE# CRE UB#/ LB# WAIT2 DQ[15:0]3 Note Read Active L L L L H L L Low-z Data out 4 Write Active L L L X L L L Low-z Data in 4 Standby Standby L X H X X L X High-z High-z 5, 6 No operation Idle L X L X X L X Low-z X 4, 6 Configuration register write Active L L L H L H X Low-z High-z Configuration register read Active LL LL H H L Low-z Config. Reg.out DPD Deep Power-down L X H X X X X High-z High-z 7 Burst Mode BCR[15]=0 Power CLK1 ADV# CE# OE# WE# CRE UB#/ LB# WAIT2 DQ[15:0]3 Note Async read Active L L L L H L L Low-z Data out 4, 8 Async write Active L L L X L L L Low-z Data in 4 Standby Standby L X H X X L X High-z High-z 5, 6 No operation Idle L X L X X L X Low-z X 4, 6 Initial burst read Active L L X H L L Low-z X 4, 9 Initial burst write Active L L H L L X Low-z X 4, 9 Burst continue Active H L X X X L Low-z Data out or Data in 4, 9 Burst suspend Active X X L H X X X Low-z High-z 4, 9 Configuration register write Active L L H L H X Low-z High-z 9, 10 Configuration register read Active L L L H H L Low-z Config. Reg.out 9, 10 DPD Deep Power-down L X H X X X X High-z High-z 7 |
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