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V54C316162VC Datasheet(PDF) 10 Page - Mosel Vitelic, Corp |
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V54C316162VC Datasheet(HTML) 10 Page - Mosel Vitelic, Corp |
10 / 22 page 10 V54C316162VC Rev. 1.4 December 2001 MOSEL VITELIC V54C316162VC AC Characteristics (1,2,3) TA =0 to 70°C; VSS =0V; VCC =3.3 V ± 0.3 V, tT =1 ns # Symbol Parameter Limit Values Unit -5 -55 -6 -7 Min. Max. Min. Max. Min. Max. Min. Max. Clock and Clock Enable tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 5 10 – – 5.5 10 – – 6 10 – – 7 10 – – ns ns tCK Clock Frequency CAS Latency = 3 CAS Latency = 2 – – 200 100 – – 183 100 – – 166 100 – – 143 100 MHz MHz tAC Access Time from Clock CAS Latency = 3 CAS Latency = 2 – – 5 7 – – 5.3 7 – – 5.5 7 – – 5.5 7 ns ns 2 3 tCH Clock High Pulse Width 2.5 – 2.5 – 2.5 – 2.5 – ns tCL Clock Low Pulse Width 2.5 – 2.5 – 2.5 – 2.5 – ns tT Transition time 1 10110 1 10110 ns Setup and Hold Times tCMDS Command Setup Time 2 – 2 – 2 – 2 – ns 4 tAS Address Setup Time 2 – 2 – 2 – 2 – ns 4 tDS Data In Setup Time 2 – 2 – 2 – 2 – ns 4 tCKS CKE Setup Time 2 – 2 – 2 – 2 – ns 4 tCMDH Command Hold Time 1 – 1 – 1 – 1 – ns 4 tAH Address Hold Time 1 – 1 – 1 – 1 – ns 4 tDH Data In Hold Time 1 – 1 – 1 – 1 – ns 4 tCKH CKE Hold Time 1 – 1 – 1 – 1 – ns 4 Common Parameters tRCD Row to Column Delay Time 15 – 16.5 – 18 – 18 – ns 5 tRAS Row Active Time 40 100K45 100K48 100K48 100K ns 5 tRC Row Cycle Time 60 – 63 – 66 – 70 – ns 5 tRP Row Precharge Time 15 – 17 – 18 – 21 – ns 5 tRRD Activate(a) to Activate(b) Com- mand period 10 – 11 – 12 – 14 – ns 5 tCCD CAS(a) to CAS(b) Command pe- riod 1 – 1 – 1 – 1 – CLK tRCS Mode Register Set-up time 10 – 11 – 12 – 14 – ns tSB Power Down Mode Entry Time 050 5.5 0607 ns tCDL Last data in to new column ad- dress delay 5 – 5.5 – 6 – 7 – ns |
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