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ADS7950SDBTR Datasheet(PDF) 8 Page - Texas Instruments |
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ADS7950SDBTR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 43 page TIMING REQUIREMENTS (see Figure 43, Figure 44, Figure 45, and Figure 46) ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 SLAS605 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 (continued) +VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ALARM SETTING Higher threshold range 000 FF Hex Lower threshold range 000 FF Hex DIGITAL INPUT/OUTPUT Logic family CMOS VIH 0.7*(+VBD) VIL +VBD = 5 V 0.8 Logic level VIL +VBD = 3 V 0.4 V VOH At Isource = 200 µA Vdd-0.2 VOL At Isink = 200 µA 0.4 Data format MSB First POWER SUPPLY REQUIREMENTS +VA supply voltage 2.7 3.3 5.25 V +VBD supply voltage 1.7 3.3 5.25 V At +VA = 2.7 to 3.6 V and 1MHz throughput 1.8 mA At +VA = 2.7 to 3.6 V static state 1.05 mA Supply current (normal mode) At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 mA At +VA = 4.7 to 5.25 V static state 1.1 1.5 mA Power-down state supply current 1 µA +VBD supply current +VA = 5.25V, fs = 1MHz 1 mA Power-up time 1 µSec Invalid conversions after power up or 1 Numbers reset TEMPERATURE RANGE Specified performance –40 125 °C All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified) PARAMETER TEST CONDITIONS(1)(2) MIN TYP MAX UNIT +VBD = 1.8 V 16 tconv Conversion time +VBD = 3 V 16 SCLK +VBD = 5 V 16 +VBD = 1.8 V 40 Minimum quiet sampling time needed from bus tq +VBD = 3 V 40 ns 3-state to start of next conversion +VBD = 5 V 40 +VBD = 1.8 V 38 td1 Delay time, CS low to first data (DO–15) out +VBD = 3 V 27 ns +VBD = 5 V 17 +VBD = 1.8 V 8 tsu1 Setup time, CS low to first rising edge of SCLK +VBD = 3 V 6 ns +VBD = 5 V 4 +VBD = 1.8 V 35 td2 Delay time, SCLK falling to SDO next data bit valid +VBD = 3 V 27 ns +VBD = 5 V 17 (1) 1.8V specifications apply from 1.7V to 1.9V, 3V specifications apply from 2.7V to 3.6V, 5V specifications apply from 4.75V to 5.25V. (2) With 50-pF load 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958, ADS7959, ADS7960, ADS7961 |
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