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ADS1282 Datasheet(PDF) 5 Page - Texas Instruments |
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ADS1282 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 52 page  TIMING DIAGRAM SCLK DIN DOUT t SCLK t SPWH t SCDL t DIST t DIHD t SPWL t SCDL t DOHD t DOPD TIMING REQUIREMENTS ADS1282 www.ti.com ................................................................................................................................................. SBAS418D – SEPTEMBER 2007 – REVISED JULY 2008 ELECTRICAL CHARACTERISTICS (continued) Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, High-Resolution Mode, and fDATA = 1000SPS, unless otherwise noted. ADS1282 PARAMETER CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVSS –2.6 0 V AVDD AVSS + 4.75 AVSS + 5.25 V DVDD 1.65 3.6 V High-resolution mode 4.5 6.5 |mA| Low-power mode 3 4.2 |mA| AVDD, AVSS current Standby mode 1 15 | µA| Power-down mode 1 15 | µA| All modes 0.6 0.8 mA Modulator mode 0.1 mA DVDD current Standby mode 25 50 µA Power-down mode(12) 1 15 µA High-reolution mode 25 35 mW Low-power mode 17 25 mW Power dissipation Standby mode 90 250 µW Power-down mode 10 125 µW (12) CLK input stopped. At TA = –40°C to +85°C and DVDD = 1.65V to 3.6V, unless otherwise noted. PARAMETER DESCRIPTION MIN MAX UNITS tSCLK SCLK period 2 16 1/fCLK tSPWH, L SCLK pulse width, high and low(1) 0.8 10 1/fCLK tDIST DIN valid to SCLK rising edge: setup time 50 ns tDIHD Valid DIN to SCLK rising edge: hold time 50 ns tDOPD SCLK falling edge to valid new DOUT: propagation delay(2) 100 ns tDOHD SCLK falling edge to DOUT invalid: hold time 0 ns Final SCLK rising edge of command to first SCLK rising edge for register read/write tSCDL 24 1/fCLK data. (Also between consecutive commands.) (1) Holding SCLK low for 64 DRDY falling edges resets the serial interface. (2) Load on DOUT = 20pF || 100k Ω. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS1282 |
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