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ADS5483IRGCRG4 Datasheet(PDF) 5 Page - Texas Instruments

Part # ADS5483IRGCRG4
Description  16-Bit, 80/105/135-MSPS Analog-to-Digital Converters
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS5483IRGCRG4 Datasheet(HTML) 5 Page - Texas Instruments

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ADS5481
ADS5482, ADS5483
www.ti.com ...................................................................................................................................................................................................... SLAS565 – JUNE 2008
ELECTRICAL CHARACTERISTICS (ADS5481, ADS5482, ADS5483) (continued)
Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,
sampling rate = Max Rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted.
ADS5481
ADS5482
ADS5483
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
DYNAMIC ACCURACY
No Missing Codes,
DNL
Differential linearity error
-0.99
±0.5
1.0
-0.99
±0.5
1.0
-0.99
±0.5
1.0
LSB
fIN = 30 MHz
INL
Integral linearity error
fIN = 30 MHz
-10
±3
+10
-10
±3
+10
-10
±3
+10
LSB
Offset error
-15
15
-15
15
-15
15
mV
Offset temperature coefficient
-0.02
-0.02
-0.02
mV/°C
Gain error
-6
±2
6
-6
±2
6
-6
±2
6
%FS
Gain temperature coefficient
-0.01
-0.01
-0.01
mV/°C
POWER SUPPLY
IAVDD5
5-V analog
316
TBD
316
TBD
317
330
mA
VIN = full-scale, fIN = 30
IAVDD3
3.3-V analog
131
TBD
131
TBD
133
150
mA
MHz,
fS = Max Rated, Normal
IDVDD3
3.3-V digital/LVDS
60
TBD
60
TBD
60
65
mA
Operation
Total power dissipation
2.2
TBD
2.2
TBD
2.2
2.35
W
IAVDD5
5-V analog
98
98
98
mA
IAVDD3
3.3-V analog
35
35
35
mA
Light Sleep Mode
(PDWNF=H, PDWNS=L)
IDVDD3
3.3-V digital/LVDS
0.07
0.07
0.07
mA
Total power dissipation
605
TBD
605
TBD
605
680
mW
IAVDD5
5-V analog
13
13
13
mA
IAVDD3
3.3-V analog
2
2
2
mA
Deep Sleep Mode
(PDWNF=L, PDWNS=H)
IDVDD3
3.3-V digital/LVDS
0.07
0.07
0.07
mA
Total power dissipation
70
TBD
70
TBD
70
100
mW
Fast Wakeup Time (Light
From PDWNF disabled
600
600
600
µS
Sleep)
Slow Wakeup Time (Deep
From PDWNS disabled
6
6
6
mS
Sleep)
AVDD5 supply
Power-supply rejection ratio,
60
60
60
dB
Without 0.1-
µF board supply
AVDD3 supply
80
80
80
dB
PSRR
capacitors, with 1-MHz
supply noise (see
95
95
95
DVDD3 supply
dB
Figure 48)
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
TBD
81
TBD
80.5
77
79
fIN = 30 MHz
TBD
80.6
TBD
80.5
77
79
SNR
Signal-to-noise ratio
fIN = 70 MHz
80.1
79.8
78.6
dBFS
fIN = 100 MHz
79.6
79.1
78.2
fIN = 130 MHz
77.8
fIN = 10 MHz
TBD
98
TBD
98
87
97
fIN = 30 MHz
TBD
97
TBD
97
87
97
SFDR
Spurious-free dynamic range
fIN = 70 MHz
94
93
95
dBc
fIN = 100 MHz
92
93
88
fIN = 130 MHz
85
fIN = 10 MHz
TBD
108
TBD
107
87
102
fIN = 30 MHz
TBD
101
TBD
105
87
99
HD2
Second-harmonic
fIN = 70 MHz
100
101
95
dBc
fIN = 100 MHz
99
100
92
fIN = 130 MHz
85
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): ADS5481 ADS5482, ADS5483


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