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UCC28070PWR Datasheet(PDF) 4 Page - Texas Instruments |
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UCC28070PWR Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 39 page  www.ti.com UCC28070 SLUS794A – NOVEMBER 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range −40 °C < T A < 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 75 kΩ, RDMX = 68.1 k Ω, RRDM = RSYN = 100 kΩ, CCDR = 2.2 nF, CSS = CVREF = 0.1 µF, CVCC = 1 µF, (unless otherwise noted) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Clock Synchronization VCDR SYNC enable threshold Measured at CDR (rising) 5 5.25 V VCDR = 6 V, Measured from RDM (rising) to SYNC propagation delay 50 100 ns GDx (rising) SYNC threshold (Rising) VCDR = 6 V, Measured at RDM 1.2 1.5 V SYNC threshold (Falling) VCDR = 6 V, Measured at RDM 0.4 0.7 Positive pulse width 0.2 µs SYNC pulses Maximum duty cycle (2) 50 % Voltage Amplifier VSENSE voltage In regulation, TA = 25°C 2.97 3 3.03 V VSENSE voltage In regulation 2.94 3 3.06 VSENSE input bias current In regulation 250 500 nA VAO high voltage VSENSE = 2.9 V 4.8 5 5.2 V VAO low voltage VSENSE = 3.1 V 0.05 0.50 gMV VAO transconductance 2.8 V < VSENSE < 3.2 V, VAO = 3 V 70 µS VAO sink current, overdriven limit VSENSE = 3.5 V, VAO = 3 V 30 VAO source current, overdriven VSENSE = 2.5 V, VAO = 3 V, SS = 3 V −30 µA VAO source current, VSENSE = 2.5 V, VAO = 3 V −130 overdriven limit + ISRC Measured as VSENSE (falling) / VSENSE Slew-rate correction threshold 92 93 95 % (regulation) Slew-rate correction hysteresis Measured at VSENSE (rising) 3 9 mV Measured at VAO, in addition to VAO ISRC Slew-rate correction current −100 µA source current. Slew-rate correction enable threshold Measured at SS (rising) 4 V VAO discharge current VSENSE = 0.5 V, VAO = 1 V 10 µA Soft Start ISS SS source current VSENSE = 0.9 V, SS = 1 V −10 µA Adaptive source current VSENSE = 2.0 V, SS = 1 V −1.5 -2.5 mA Adaptive SS disable Measured as VSENSE – SS -30 0 30 mV SS sink current VSENSE = 0.5 V, SS = 0.2 V 0.5 0.9 mA (2) Due to the influence of the synchronization pulse width on the programmability of the maximum PWM switching duty cycle (DMAX) it is recommended to minimize the synchronization signal's duty cycle. 4 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): UCC28070 |
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