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TPS3808G19DBVTG4 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS3808G19DBVTG4 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 18 page Adjustable Voltage Version Fixed Voltage Version Reset Logic Timer + − 90k V DD V DD GND 0.4V V REF SENSE MR C T RESET TPS3808G01 Adjustable Voltage Reset Logic Timer + − 90k V DD V DD GND 0.4V V REF SENSE MR C T RESET R 1 R 2 R 1 + R2 = 4MΩ PIN ASSIGNMENTS RESET GND MR 6 5 4 V DD SENSE C T 1 2 3 Power PAD V DD SENSE C T RESET GND MR 1 2 3 6 5 4 TPS3808 SBVS050I – MAY 2004 – REVISED AUGUST 2008........................................................................................................................................................... www.ti.com FUNCTIONAL BLOCK DIAGRAMS Figure 1. Adjustable and Fixed Voltage Versions DBV PACKAGE DRV PACKAGE SOT23 2mm × 2mm QFN (TOP VIEW) (TOP VIEW) Table 1. TERMINAL FUNCTIONS TERMINAL SOT23 (DBV) NAME PIN NO. DESCRIPTION RESET 1 RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET will remain low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pull-up resistor from 10k Ω to 1MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD. GND 2 Ground MR 3 Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90kΩ pull-up resistor. CT 4 Reset period programming pin. Connecting this pin to VDD through a 40kΩ to 200kΩ resistor or leaving it open results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced capacitor ≥ 100pF gives a user-programmable delay time. See the Selecting the Reset Delay Time section for more information. SENSE 5 This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage VIT, then RESET is asserted. VDD 6 Supply voltage. It is good analog design practice to place a 0.1 µF ceramic capacitor close to this pin. PowerPAD PowerPAD. Connect to ground plane to enhance thermal performance of package. 4 Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Link(s): TPS3808 |
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