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TIMING CHARACTERISTICS

N

N+1

N+2

N+3

N+4

N

N−1

N−2

N−3

N + 1

N

N + 2

N + 3

N + 4

CLK, CLK

D[12:0],

OVR, OVR

DRY, DRY

AIN

T0073-01

TIMING CHARACTERISTICS

ADS5444

SLWS162A – AUGUST 2005 – REVISED FEBRUARY 2006

Figure 1. Timing Diagram

Min, Typ, Max over full temperature range, 50% clock duty cycle, sampling rate = 250 MSPS, AV

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperature delay

500

ps

Clock slope independent aperture uncertainty (jitter)

200

fs RMS

Latency

4

cycles

Clock Input

Clock period

4

ns

Clock pulsewidth high

2

ns

Clock pulsewidth low

2

ns

Clock to DataReady (DRY)

Clock rising to DataReady falling

1.1

ns

Clock rising to DataReady rising

2.7

3.1

3.5

ns

Data rise time (20% to 80%)

0.6

ns

Data fall time(80% to 20%)

0.6

ns

Data valid to clock (setup time)

3.1

ns

Clock to invalid Data (hold time)

0.2

ns

Data valid to DRY

1.7

2

ns

DRY to invalid Data

0.9

1.3

ns

(1)

(2)

Data is updated with clock falling edge or DRY rising edge.

6

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