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SN65LVDS315 Datasheet(PDF) 9 Page - Texas Instruments |
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SN65LVDS315 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 34 page www.ti.com VS and HS Timing to Generate the Correct Control Signals CLK D[0:8] VS HS OUT (Serial) B B P1 P2 P3 P4 P5 B B SOF1 SOF2 SOF3 SOF4 P1 CLK D[0:8] OUT (Serial) VS HS B B P1 P2 P3 P4 P5 P6 B B SOL1 SOL2 SOL3 SOL4 P1 P2 CLK D[0:8] VS HS OUT (Serial) P480 B B B B B B B B P476 P477 P478 P479 P480 EOL1 EOL2 EOL3 EOL4 CLK D[0:8] VS HS OUT (Serial) P480 B B B B B B B B P476 P477 P478 P479 P480 EOF1 EOF2 EOF3 EOF4 CLK D[0:8] VS HS OUT (Serial) B B P1 P2 P3 P4 P479 B B 480 B B B B B B B B B P1 P2 P3 P4 P5 180 B B B B B B B B B B B P1 P2 P3 P4 P5 B B SOF1 SOF2 SOF3 SOF4 P1 176 P477 P478 P479 P480 EOL1 EOL2 EOL3 EOL4 B B B P477 P478 P479 P480 SOL1 SOL2 SOL3 SOL4 P1 476 EOF1 EOF2 EOF3 EOF4 B B B SOF1 SOF2 SOF3 SOF4 P1 Line1 BlankingLine1 Line2 BlankingLastLine NewFrame SN65LVDS315 SLLS881A – DECEMBER 2007 – REVISED MARCH 2008 The VS and HS timing received from camera sensors varies. The SN65LVDS315 responds in the following way: Frame Start and Line Start Frame start is indicated by a VS transition from low to high. The rising edge on HS following the VS high transition or occurring simultaneously with VS indicates the first valid data line and initiates the transmission of SOF. Any additional rising edge on HS initiates transmission of SOL until VS is de-asserted to low. Line End and Frame End A falling edge of HS indicates the end of a valid line, causing the SN65LVDS315 to transmit the EOL data word. If HS and VS are set low with the same DCLK cycle, the device will transmit EOF instead of EOL. Ideally, the VS and HS falling edge occur during the same clock period. In such case, the MODE input can be kept low (MODE=0), and the response of the SN65LVDS315 output to the parallel input data looks like the following: Figure 6. VS and HS Timing Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s) :SN65LVDS315 |
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