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AD5750BCPZ Datasheet(PDF) 8 Page - Analog Devices |
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AD5750BCPZ Datasheet(HTML) 8 Page - Analog Devices |
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8 / 25 page  AD5750 Preliminary Technical Data Rev. P rC | Page 8 of 25 TIMING CHARACTERISTICS AVDD/AVSS=±12V (+/-10%) to ±24V (+/-10%) , DVCC =2.7 V to 5.5 V, GND = 0 V. RL = 2 kΩ, CL = 200 pF, IOUT : RL = 300Ω, HL = 50mH; All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2 Limit at TMIN, TMAX Unit Description t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 13 ns min 16th SCLK falling edge to SYNC rising edge t6 13 ns min Minimum SYNC high time (WRITE MODE) t7 6 ns min Data setup time t8 0 ns min Data hold time t10 , t9 1 μs max CLEAR pulse high/low activation time t11 25 ns min Minimum SYNC high time (READ MODE) t12 25 ns max SCLK rising edge to SDO valid (SDO CL=20pf ) 1 Guaranteed by characterization. Not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 200µA IOL 200µA IOH VOH(min)-VOL(max) TO OUTPUT PIN CL 15pF 2 SDO Load Timing. |
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