V55C2128164V datasheet(4/44 Pages) MOSEL

Part #	V55C2128164V

Description	128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16

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Manufacturer	MOSEL [Mosel Vitelic, Corp]

Direct Link	http://www.moselvitelic.com

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V55C2128164V(T/B) Rev. 1.2 August 2002

MOSEL VITELIC

V55C2128164V(T/B)

Description

The V55C2128164V(T/B) is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 16. The

V55C2128164V(T/B) achieves high speed data transfer rates up to 166 MHz by employing a chip architecture

that prefetches multiple bits and then synchronizes the output data to a system clock

All of the control, address, data input and output circuits are synchronized with the positive edge of an ex-

ternally supplied clock.

Operating the four memory banks in an interleaved fashion allows random access operation to occur at

higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is

possible depending on burst length, CAS latency and speed grade of the device.

Signal Pin Description

Type

Signal

Polarity

Function

CLK

Input

Pulse

Positive

Edge

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the

clock.

CKE

Input

Level

Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby

initiates either the Power Down mode or the Self Refresh mode.

CS

Input

Pulse

Active Low CS enables the command decoder when low and disables the command decoder when

high. When the command decoder is disabled, new commands are ignored but previous

operations continue.

RAS, CAS

WE

Input

Pulse

Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the

command to be executed by the SDRAM.

A0 - A11

Input

Level

—

During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)

when sampled at the rising clock edge.CAn depends from the SDRAM organization:

• 8M x 16 SDRAM CA0–CA8.

In addition to the column address, A10(=AP) is used to invoke autoprecharge operation

at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and

BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.

During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1

to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are

used to define which bank to precharge.

BA0,

BA1

Input

Level

—

Selects which bank is to be active.

DQx

Input

Output

Level

—

Data Input/Output pins operate in the same manner as on conventional DRAMs.

LDQM

UDQM

Input

Pulse

Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-

pled high. In Read mode, DQM has a latency of two clock cycles and controls the output

buffers like an output enable. In Write mode, DQM has a latency of zero and operates as

a word mask by allowing input data to be written if it is low but blocks the write operation

if DQM is high.

VCC, VSS

Supply

Power and ground for the input buffers and the core logic.

VCCQ

VSSQ

Supply

—

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

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