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CC1110F8RSP Datasheet(PDF) 10 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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CC1110F8RSP Datasheet(HTML) 10 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
10 / 240 page CC1110Fx / CC1111Fx SWRS033E Page 10 of 239 7 Electrical Specifications 7.1 Current Consumption TA = 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1110EM reference design ([1]). Parameter Min Typ Max Unit Condition Digital regulator on. High speed crystal oscillator and low power RCOSC running. No peripherals running. Low CPU activity: No flash access (i.e. only cache hit), no RAM access 5.0 mA System clock running at 26 MHz. Active mode, full speed (high speed crystal oscillator) 1. Low CPU activity. 4.8 mA System clock running at 24 MHz. CC1111Fx runs on 48 MHz crystal giving 24 MHz system clock Active mode, full speed (HS RCOSC) 1. Low CPU activity. 2.5 mA System clock running at 13 MHz. Digital regulator on. HS RCOSC and low power RCOSC running. No peripherals running. Low CPU activity: No flash access (i.e. only cache hit), no RAM access Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in RX mode (sensitivity optimized MDMCFG2.DEM_DCFILT_OFF=1) 19 19.5 16.2 mA mA mA 1.2 kBaud, input at sensitivity limit, system clock at 26 MHz. 1.2 kBaud, input at sensitivity limit, system clock at 24 MHz 1.2 kBaud, input at sensitivity limit, system clock at 203 kHz. 19 19.4 mA mA 1.2 kBaud, input well above sensitivity limit, system clock at 26 MHz 1.2 kBaud, input well above sensitivity limit, system clock at 24 MHz 19 16.2 mA mA 38.4 kBaud, input at sensitivity limit, system clock at 26 MHz. 38.4 kBaud, input at sensitivity limit, system clock at 203 kHz. 19 mA 38.4 kBaud, input well above sensitivity limit, system clock at 26 MHz. 20 21 17.2 mA mA mA 250 kBaud, input at sensitivity limit, system clock at 26 MHz 250 kBaud, input at sensitivity limit, system clock at 24 MHz. 250 kBaud, input at sensitivity limit, system clock at 1.625 MHz. Active mode with radio in RX, 315 MHz 20 20 mA mA 250 kBaud, input well above sensitivity limit, system clock at 26 MHz. 250 kBaud, input well above sensitivity limit, system clock at 24 MHz. 1 Note: In order to reduce the current consumption in active mode, the clock speed can be reduced by setting CLKCON.CLKSPD ≠ 000 (see section 13.1 for details). Figure 1 shows typical current consumption in active mode for different clock speeds |
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